Reduced size of preproc right shift

2022-12-30 06:47:40 -08:00 · 2022-12-30 06:47:40 -08:00 · dba3ffe767
commit dba3ffe767
parent 0e9bd5dab5
1 changed files with 2 additions and 1 deletions
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@ -70,7 +70,8 @@ module fdivsqrtpreproc (
    logic  AsE, BsE, ALTBE, NegQuotE;
    logic  [`XLEN-1:0]  AE, BE;
    logic  [`XLEN-1:0] PosA, PosB;
-    logic  [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;
+    logic  [`DIVBLEN:0] ZeroDiff, IntBits;
+    logic  [`LOGRK-1:0] RightShiftX;

    // Extract inputs, signs, zero, depending on W64 mode if applicable
    assign signedDiv = ~Funct3E[0];