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atomic cleanup.

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This commit is contained in:
Ross Thompson 2022-03-10 18:56:37 -06:00
parent 257015a2df
commit 7f0c5cc847
3 changed files with 8 additions and 11 deletions
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3
pipelined/src/lsu/atomic.sv
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@ -41,7 +41,6 @@ module atomic (
input logic [1:0] LSUAtomicM,
input logic [1:0] PreLSURWM,
input logic IgnoreRequest,
input logic DTLBMissM,
output logic [`XLEN-1:0] FinalAMOWriteDataM,
output logic SquashSCW,
output logic [1:0] LSURWM);
@ -52,7 +51,7 @@ module atomic (
amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]),
.result(AMOResult));
mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
assign MemReadM = PreLSURWM[1] & ~(IgnoreRequest) & ~DTLBMissM; // *** is DTLBMiss needed; might be par tof ignorerequest
assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
.SquashSCW, .LSURWM);

12
pipelined/src/lsu/interlockfsm.sv
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@ -56,7 +56,7 @@ module interlockfsm(
logic AnyCPUReqM;
typedef enum logic[2:0] {STATE_T0_READY,
STATE_T0_REPLAY,
STATE_T1_REPLAY,
STATE_T3_DTLB_MISS,
STATE_T4_ITLB_MISS,
STATE_T5_ITLB_MISS,
@ -82,13 +82,13 @@ module interlockfsm(
else if(ToITLBMiss) InterlockNextState = STATE_T5_ITLB_MISS;
else if(ToBoth) InterlockNextState = STATE_T7_DITLB_MISS;
else InterlockNextState = STATE_T0_READY;
STATE_T0_REPLAY: if(DCacheStallM) InterlockNextState = STATE_T0_REPLAY;
STATE_T1_REPLAY: if(DCacheStallM) InterlockNextState = STATE_T1_REPLAY;
else InterlockNextState = STATE_T0_READY;
STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY;
STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T1_REPLAY;
else InterlockNextState = STATE_T3_DTLB_MISS;
STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY;
else InterlockNextState = STATE_T4_ITLB_MISS;
STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY;
STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T1_REPLAY;
else InterlockNextState = STATE_T5_ITLB_MISS;
STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS;
else InterlockNextState = STATE_T7_DITLB_MISS;
@ -122,12 +122,12 @@ module interlockfsm(
endcase
end
assign SelReplayMemE = (InterlockCurrState == STATE_T0_REPLAY & DCacheStallM) |
assign SelReplayMemE = (InterlockCurrState == STATE_T1_REPLAY & DCacheStallM) |
(InterlockCurrState == STATE_T3_DTLB_MISS & DTLBWriteM) |
(InterlockCurrState == STATE_T5_ITLB_MISS & ITLBWriteF);
assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
(InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
assign IgnoreRequestTLB = (InterlockCurrState == STATE_T0_READY & (ITLBMissOrDAFaultF | DTLBMissOrDAFaultM));
assign IgnoreRequestTrapM = (InterlockCurrState == STATE_T0_READY & (TrapM)) |
((InterlockCurrState == STATE_T0_REPLAY) & (TrapM));
((InterlockCurrState == STATE_T1_REPLAY) & (TrapM));
endmodule

4
pipelined/src/lsu/lsu.sv
View File

@ -259,12 +259,10 @@ module lsu (
/////////////////////////////////////////////////////////////////////////////////////////////
// Atomic operations
/////////////////////////////////////////////////////////////////////////////////////////////
// *** why does this need DTLBMissM?
if (`A_SUPPORTED) begin:atomic
atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .LSUWriteDataM, .LSUPAdrM,
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
.DTLBMissM, .FinalAMOWriteDataM, .SquashSCW, .LSURWM);
.FinalAMOWriteDataM, .SquashSCW, .LSURWM);
end else begin:lrsc
assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = LSUWriteDataM;
end