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Fixed early termination on fdivsqrt

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This commit is contained in:
David Harris 2022-12-23 00:53:55 -08:00
parent 0505f1fd37
commit e061bacc9d
1 changed files with 3 additions and 3 deletions
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6
pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
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@ -115,10 +115,10 @@ module fdivsqrtfsm(
step <= cycles;
if (SpecialCaseE) state <= #1 DONE;
else state <= #1 BUSY;
end else if (state == BUSY) begin
if (step == 1) state <= #1 DONE;
end else if (state == BUSY) begin
if (step == 1 | WZeroM) state <= #1 DONE; // finished steps or terminate early on zero residual
step <= step - 1;
end else if ((state == DONE) | (WZeroM & (state == BUSY))) begin
end else if (state == DONE) begin
if (StallM) state <= #1 DONE;
else state <= #1 IDLE;
end