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Made SqrtE only true on square root so gating with ~MDUE can be removed)

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This commit is contained in:
David Harris 2022-12-27 10:27:07 -08:00
parent e34b8139af
commit acc9498ae2
3 changed files with 8 additions and 5 deletions
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2
pipelined/src/fpu/fctrl.sv
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@ -167,7 +167,7 @@ module fctrl (
7'b0100001: ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.s
default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // non-implemented instruction
endcase
default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // non-implemented instruction
default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
endcase
// unswizzle control bits

2
pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
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@ -65,7 +65,7 @@ module fdivsqrtfsm(
// terminate immediately on special cases
assign FSpecialCaseE = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
assign ISpecialCaseE = AZeroE | BZeroE;
assign ISpecialCaseE = AZeroE | BZeroE; // *** why is AZeroE part of this. Should other special cases be considered?
assign SpecialCaseE = MDUE ? ISpecialCaseE : FSpecialCaseE;
flopenr #(1) SpecialCaseReg(clk, reset, ~StallM, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc

9
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -66,13 +66,16 @@ module fdivsqrtpostproc(
aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0E);
if (`RADIX == 2) begin: R2EarlyTerm
logic [`DIVb+3:0] FZeroE;
logic [`DIVb+3:0] FZeroE, FZeroSqrtE, FZeroDivE;
logic [`DIVb+2:0] FirstK;
logic wfeq0E;
logic [`DIVb+3:0] WCF, WSF;
assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1));
assign FZeroE = (SqrtE & ~MDUE) ? {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0} : {3'b001,D,1'b0};
assign FZeroSqrtE = {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0}; // F for square root
assign FZeroDivE = {3'b001,D,1'b0}; // F for divide
assign FZeroE = SqrtE ? FZeroSqrtE : FZeroDivE;
// assign FZeroE = (SqrtE & ~MDUE) ? FZeroSqrtE : FZeroDivE;
csa #(`DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
assign WZeroE = weq0E|(wfeq0E & Firstun);
@ -94,7 +97,7 @@ module fdivsqrtpostproc(
// If the result is not exact, the sticky should be set
assign DivSM = ~WZeroM & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide
// Determine if sticky bit is negative // *** look for ways to optimize this
// Determine if sticky bit is negative // *** look for ways to optimize this. Shift shouldn't be needed.
assign Sum = WC + WS;
assign W = $signed(Sum) >>> `LOGR;
assign NegStickyM = W[`DIVb+3];