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Parameterized fmalza

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This commit is contained in:
David Harris 2022-08-01 16:18:02 -07:00
parent 6e78b46761
commit 8b44037f58
2 changed files with 5 additions and 7 deletions
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4
pipelined/src/fpu/fma.sv
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@ -85,8 +85,8 @@ module fma(
fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .NegSum, .InvA, .Sm, .Se, .Ss);
fmalza lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt);
fmalza #(3*`NF+6) lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt);
endmodule

8
pipelined/src/fpu/fmalza.sv
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@ -29,16 +29,14 @@
`include "wally-config.vh"
module fmalza( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
input logic [3*`NF+5:0] A, // addend
module fmalza #(WIDTH) ( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
input logic [WIDTH-1:0] A, // addend
input logic [2*`NF+3:0] Pm, // product
input logic Cin, // carry in
input logic sub,
output logic [$clog2(3*`NF+7)-1:0] SCnt // normalization shift count for the positive result
output logic [$clog2(WIDTH+1)-1:0] SCnt // normalization shift count for the positive result
);
localparam WIDTH = 3*`NF+6;
logic [WIDTH:0] F;
logic [WIDTH-1:0] B, P, G, K;
logic [WIDTH-1:0] Pp1, Gm1, Km1;