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Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0.

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Switched to even simplier PC+2/4 logic.
This commit is contained in:
Ross Thompson 2022-12-21 09:00:09 -06:00
parent a02b40cf02
commit ac94b55e74
2 changed files with 5 additions and 4 deletions
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4
pipelined/src/ifu/ifu.sv
View File

@ -299,11 +299,9 @@ module ifu (
// choose PC+2 or PC+4 based on CompressedF, which arrives later.
// Speeds up critical path as compared to selecting adder input based on CompressedF
// *** consider gating PCPlusUpperF to provide the reset.
/* -----\/----- EXCLUDED -----\/-----
assign PCPlus2or4F[0] = '0;
assign PCPlus2or4F[1] = ~reset & (CompressedF ^ PCF[1]);
assign PCPlus2or4F[`XLEN-1:2] = reset ? '0 : CompressedF & ~PCF[1] ? PCF[`XLEN-1:2] : PCPlusUpperF;
-----/\----- EXCLUDED -----/\----- */
/* -----\/----- EXCLUDED -----\/-----
assign PCPlus2or4F[1:0] = reset ? 2'b00 : CompressedF ? PCF[1] ? 2'b00 : 2'b10 : PCF[1:0];
-----/\----- EXCLUDED -----/\----- */
@ -311,12 +309,14 @@ module ifu (
// *** There is actually a bug in the regression test. We fetched an address which returns data with
// an X. This version of the code does not die because if CompressedF is an X it just defaults to the last
// option. The above code would work, but propagates the x.
/* -----\/----- EXCLUDED -----\/-----
always_comb
if(reset) PCPlus2or4F = '0;
else if (CompressedF) // add 2
if (PCF[1]) PCPlus2or4F = {PCPlusUpperF, 2'b00};
else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4
-----/\----- EXCLUDED -----/\----- */
////////////////////////////////////////////////////////////////////////////////////////////////

5
pipelined/src/uncore/plic_apb.sv
View File

@ -59,7 +59,7 @@ module plic_apb (
input logic UARTIntr,GPIOIntr,
(* mark_debug = "true" *) output logic MExtInt, SExtInt);
logic memwrite, memread, initTrans;
logic memwrite, memread;
logic [23:0] entry;
(* mark_debug = "true" *) logic [31:0] Din, Dout;
@ -130,7 +130,8 @@ module plic_apb (
// Read synchronously because a read can have side effect of changing intInProgress
if (memread)
casez(entry)
24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]};
24'h000000: Dout <= #1 32'b0; // there is no intPriority[0]
24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]};
`ifdef PLIC_NUM_SRC_LT_32
24'h001000: Dout <= #1 {{(31-`N){1'b0}},intPending,1'b0};
24'h002000: Dout <= #1 {{(31-`N){1'b0}},intEn[0],1'b0};