Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

added corrrect scr read out of uart to periph test

Browse Source
This commit is contained in:
Kip Macsai-Goren 2022-12-05 20:14:41 -08:00
parent ae32e2a9ee
commit 1d268fded4
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-periph-01.reference_output
View File

@ -440,7 +440,7 @@ FFFFFFCC # serviced low ip
00000065
00000060
00000001
00000000
000000ff
00000000
00000000
00000000
@ -488,7 +488,7 @@ FFFFFFFE
0000006e
00000060
00000001
00000000
000000ff
00000000
00000000
00000000

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
View File

@ -59,8 +59,8 @@ trap_handler: #####
#
# <offset>: <contents>
# 0x00: test ID = 0x<group_num>BEEF<intr_num>
# 0x04: mcause (low) = 0x0000000B (MEIP) or 0x00000009 (SEIP)
# 0x08: mcause (high) = 0x80000000
# 0x04: mcause (low) = 0x8000000B (MEIP) or 0x80000009 (SEIP)
# 0x08: mcause (high) = 0x00000000
# ----- If GPIO -----
# 0x0C: claim ID = 3
# 0x10: input_val