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Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE

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This commit is contained in:
David Harris 2022-12-15 08:23:34 -08:00
parent fa19a111c6
commit 2457448e29
12 changed files with 28 additions and 27 deletions
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4
pipelined/config/buildroot/wally-config.vh
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@ -70,8 +70,8 @@
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 4
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64

4
pipelined/config/fpga/wally-config.vh
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@ -72,8 +72,8 @@
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 4
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64

4
pipelined/config/rv32e/wally-config.vh
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@ -71,8 +71,8 @@
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 1
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 1
`define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64

4
pipelined/config/rv32gc/wally-config.vh
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@ -70,8 +70,8 @@
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 4
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64

4
pipelined/config/rv32i/wally-config.vh
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@ -71,8 +71,8 @@
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 4
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64

4
pipelined/config/rv32ic/wally-config.vh
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@ -70,8 +70,8 @@
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 4
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64

4
pipelined/config/rv64BP/wally-config.vh
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@ -74,8 +74,8 @@
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 64
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 4
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 0
// Address space

4
pipelined/config/rv64fpquad/wally-config.vh
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@ -72,8 +72,8 @@
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 4
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64

4
pipelined/config/rv64gc/wally-config.vh
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@ -72,8 +72,8 @@
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 4
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64

4
pipelined/config/rv64i/wally-config.vh
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@ -72,8 +72,8 @@
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 4
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64

12
pipelined/src/muldiv/intdivrestoring.sv
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@ -48,10 +48,10 @@ module intdivrestoring (
typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;
statetype state;
logic [`XLEN-1:0] W[`DIV_BITSPERCYCLE:0];
logic [`XLEN-1:0] XQ[`DIV_BITSPERCYCLE:0];
logic [`XLEN-1:0] W[`IDIV_BITSPERCYCLE:0];
logic [`XLEN-1:0] XQ[`IDIV_BITSPERCYCLE:0];
logic [`XLEN-1:0] DinE, XinE, DnE, DAbsBE, DAbsB, XnE, XInitE, WnM, XQnM;
localparam STEPBITS = $clog2(`XLEN/`DIV_BITSPERCYCLE);
localparam STEPBITS = $clog2(`XLEN/`IDIV_BITSPERCYCLE);
logic [STEPBITS:0] step;
logic Div0E, Div0M;
logic DivStartE, SignXE, SignDE, NegQE, NegWM, NegQM;
@ -91,8 +91,8 @@ module intdivrestoring (
//////////////////////////////
// initialization multiplexers on first cycle of operation
mux2 #(`XLEN) wmux(W[`DIV_BITSPERCYCLE], {`XLEN{1'b0}}, DivStartE, WNext);
mux2 #(`XLEN) xmux(XQ[`DIV_BITSPERCYCLE], XInitE, DivStartE, XQNext);
mux2 #(`XLEN) wmux(W[`IDIV_BITSPERCYCLE], {`XLEN{1'b0}}, DivStartE, WNext);
mux2 #(`XLEN) xmux(XQ[`IDIV_BITSPERCYCLE], XInitE, DivStartE, XQNext);
// registers before division steps
flopen #(`XLEN) wreg(clk, DivBusyE, WNext, W[0]);
@ -101,7 +101,7 @@ module intdivrestoring (
// one copy of divstep for each bit produced per cycle
genvar i;
for (i=0; i<`DIV_BITSPERCYCLE; i = i+1)
for (i=0; i<`IDIV_BITSPERCYCLE; i = i+1)
intdivrestoringstep divstep(W[i], XQ[i], DAbsB, W[i+1], XQ[i+1]);
//////////////////////////////

3
pipelined/testbench/testbench.sv
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@ -434,7 +434,7 @@ module riscvassertions;
initial begin
assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
assert (`S_SUPPORTED | `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support");
assert (`DIV_BITSPERCYCLE == 1 | `DIV_BITSPERCYCLE==2 | `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4");
assert (`IDIV_BITSPERCYCLE == 1 | `IDIV_BITSPERCYCLE==2 | `IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
@ -463,6 +463,7 @@ module riscvassertions;
assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS.");
assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
end
// *** DH 8/23/