Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

addins/riscv-arch-test

@@ -1 +1 @@
-Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
+Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86

pipelined/regression/regression-wally

@@ -46,7 +46,7 @@ configs = [
 ]
 def getBuildrootTC(short):
     INSTR_LIMIT = 4000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
-    MAX_EXPECTED = 246000000
+    MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt.
     if short:
         BRcmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"
         BRgrepstr=str(INSTR_LIMIT)+" instructions"

pipelined/srt/srt.sv

@@ -47,7 +47,7 @@ module srt #(parameter Nf=52) (
   input  logic       Int, // Choose integer inputss
   input  logic       Sqrt, // perform square root, not divide
   output logic       rsign,
-  output logic [Nf-1:0] Quot, Rem, // *** later handle integers
+  output logic [Nf-1:0] Quot, Rem, QuotOTFC, // *** later handle integers
   output logic [`NE-1:0] rExp,
   output logic [3:0] Flags
 );
@@ -91,6 +91,8 @@ module srt #(parameter Nf=52) (
   signcalc signcalc(.XSign, .YSign, .calcSign);
 
   srtpostproc postproc(rp, rm, Quot);
+  
+  otfc otfc(qp, qz, qm, Quot, QuotOTFC);
 endmodule
 
 module srtpostproc #(parameter N=52) (
@@ -210,9 +212,24 @@ module qacc #(parameter N=55) (
     end */
 endmodule
 
+//////////
+// otfc //
+//////////
+
+module otfc #(parameter N=52) (
+  input  logic         qp, qz, qm,
+  input  logic [N-1:0] Quot,
+  output logic [N-1:0] QuotOTFC
+);
+
+    assign QuotOTFC = Quot;
+
+endmodule
+
 /////////
 // inv //
 /////////
+
 module inv(input  logic [55:0] in, 
            output logic [55:0] out);
 

pipelined/srt/testbench.sv

@@ -44,7 +44,7 @@ module testbench;
   logic [51:0]  afrac, bfrac;
   logic [10:0]  aExp, bExp;
   logic         asign, bsign;
-  logic [51:0]  r;
+  logic [51:0]  r, rOTFC;
   logic [54:0]  rp, rm;   // positive quotient digits
  
   // Test parameters
@@ -72,7 +72,7 @@ module testbench;
                 .SrcXFrac(afrac), .SrcYFrac(bfrac), 
                 .SrcA('0), .SrcB('0), .Fmt(2'b00), 
                 .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), 
-                .Quot(r), .Rem(), .Flags());
+                .Quot(r), .QuotOTFC(rOTFC), .Rem(), .Flags());
 
   // Counter
   counter counter(clk, req, done);
@@ -117,6 +117,13 @@ module testbench;
 	      $display("failed\n");
 	      $stop;
 	    end
+    if (r !== rOTFC) // Check if OTFC works
+      begin
+        errors = errors+1;
+        $display("OTFC is %h, should be %h\n", rOTFC, r);
+        $display("failed/n");
+        $stop;
+      end
 	  if (afrac === 52'hxxxxxxxxxxxxx)
 	    begin
  	      $display("%d Tests completed successfully", testnum);