forked from Github_Repos/cvw
Renamed IFU and LSU stalls.
This commit is contained in:
Ross Thompson
parent
03021765a6
commit
2cc4d66ded
@ -306,12 +306,12 @@ connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsoc/core/hzu/CS
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe59]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
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connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsoc/core/hzu/LSUStallM ]]
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connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsoc/core/hzu/LSUStallW ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe60]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
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connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IFUStallF ]]
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connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IFUStallD ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe61]
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@ -10,7 +10,7 @@ add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/Ret
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add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/StoreStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallW
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
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@ -191,7 +191,7 @@ add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWRITED
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add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallW
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM
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@ -15,7 +15,7 @@ add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
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add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallW
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/ExceptionM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
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@ -185,7 +185,7 @@ add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/i
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/PAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallW
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM
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@ -9,8 +9,8 @@ add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPP
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallW
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
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@ -218,7 +218,7 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
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add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
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add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
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add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallW
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add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
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add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
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add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
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@ -34,7 +34,7 @@ module hazard(
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// Detect hazards
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(* mark_debug = "true" *) input logic BPPredWrongE, CSRWriteFenceM, RetM, TrapM,
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(* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
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(* mark_debug = "true" *) input logic LSUStallM, IFUStallF,
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(* mark_debug = "true" *) input logic LSUStallW, IFUStallD,
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(* mark_debug = "true" *) input logic FCvtIntStallD, FPUStallD,
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(* mark_debug = "true" *) input logic DivBusyE,FDivBusyE,
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(* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM,
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@ -86,8 +86,8 @@ module hazard(
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assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause;
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// WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap
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assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM));
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//assign StallWCause = (IFUStallF | LSUStallM) & ~TrapM;
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assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);
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//assign StallWCause = (IFUStallD | LSUStallW) & ~TrapM;
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assign StallWCause = (IFUStallD & ~FlushDCause) | (LSUStallW & ~FlushWCause);
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// Stall each stage for cause or if the next stage is stalled
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assign #1 StallF = StallFCause | StallD;
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@ -38,7 +38,7 @@ module ifu (
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// Bus interface
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(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA,
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR,
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(* mark_debug = "true" *) output logic IFUStallF,
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(* mark_debug = "true" *) output logic IFUStallD,
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(* mark_debug = "true" *) output logic [2:0] IFUHBURST,
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(* mark_debug = "true" *) output logic [1:0] IFUHTRANS,
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(* mark_debug = "true" *) output logic [2:0] IFUHSIZE,
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@ -113,7 +113,7 @@ module ifu (
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logic SelNextSpillF;
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logic ICacheFetchLine;
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logic BusStall;
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logic ICacheStallF, IFUCacheBusStallF;
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logic ICacheStallF, IFUCacheBusStallD;
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logic GatedStallD;
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(* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF;
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// branch predictor signal
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@ -129,7 +129,7 @@ module ifu (
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if(`C_SUPPORTED) begin : SpillSupport
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spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .Flush(FlushD), .PCF, .PCPlus4F, .PCNextF, .InstrRawF(InstrRawF),
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.InstrDAPageFaultF, .IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill,
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.InstrDAPageFaultF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill,
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.SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
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end else begin : NoSpillSupport
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assign PCNextFSpill = PCNextF;
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@ -273,8 +273,8 @@ module ifu (
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assign InstrRawF = IROMInstrF;
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end
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assign IFUCacheBusStallF = ICacheStallF | BusStall;
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assign IFUStallF = IFUCacheBusStallF | SelNextSpillF;
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assign IFUCacheBusStallD = ICacheStallF | BusStall;
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assign IFUStallD = IFUCacheBusStallD | SelNextSpillF;
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assign GatedStallD = StallD & ~SelNextSpillF;
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flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
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@ -40,7 +40,7 @@ module spillsupport #(parameter CACHE_ENABLED)
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input logic [`XLEN-1:2] PCPlus4F,
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input logic [`XLEN-1:0] PCNextF,
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input logic [31:0] InstrRawF,
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input logic IFUCacheBusStallF,
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input logic IFUCacheBusStallD,
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input logic ITLBMissF,
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input logic InstrDAPageFaultF,
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output logic [`XLEN-1:0] PCNextFSpill,
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@ -67,7 +67,7 @@ module spillsupport #(parameter CACHE_ENABLED)
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mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill));
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assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
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assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF));
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assign TakeSpillF = SpillF & ~IFUCacheBusStallD & ~(ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF));
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always_ff @(posedge clk)
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if (reset | Flush) CurrState <= #1 STATE_READY;
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@ -77,7 +77,7 @@ module spillsupport #(parameter CACHE_ENABLED)
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case (CurrState)
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STATE_READY: if (TakeSpillF) NextState = STATE_SPILL;
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else NextState = STATE_READY;
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STATE_SPILL: if(IFUCacheBusStallF | StallF) NextState = STATE_SPILL;
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STATE_SPILL: if(IFUCacheBusStallD | StallF) NextState = STATE_SPILL;
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else NextState = STATE_READY;
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default: NextState = STATE_READY;
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endcase
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@ -85,7 +85,7 @@ module spillsupport #(parameter CACHE_ENABLED)
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assign SelSpillF = (CurrState == STATE_SPILL);
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assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF) |
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(CurrState == STATE_SPILL & IFUCacheBusStallF);
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(CurrState == STATE_SPILL & IFUCacheBusStallD);
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assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF;
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assign SavedInstr = CACHE_ENABLED ? InstrRawF[15:0] : InstrRawF[31:16];
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@ -40,7 +40,7 @@
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module lsu (
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input logic clk, reset,
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input logic StallM, FlushM, StallW, FlushW,
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output logic LSUStallM,
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output logic LSUStallW,
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// connected to cpu (controls)
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input logic [1:0] MemRWM,
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input logic [2:0] Funct3M,
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@ -103,7 +103,7 @@ module lsu (
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logic [1:0] LSUAtomicM;
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(* mark_debug = "true" *) logic [`XLEN+1:0] IHAdrM;
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logic GatedStallW;
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logic DCacheStallM;
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logic DCacheStallW;
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logic CacheableM;
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logic BusStall;
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logic HPTWStall;
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@ -120,7 +120,7 @@ module lsu (
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flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
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assign IEUAdrExtM = {2'b00, IEUAdrM};
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assign IEUAdrExtE = {2'b00, IEUAdrE};
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assign LSUStallM = DCacheStallM | HPTWStall | BusStall;
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assign LSUStallW = DCacheStallW | HPTWStall | BusStall;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// HPTW(only needed if VM supported)
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@ -130,7 +130,7 @@ module lsu (
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if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
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hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
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.DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM,
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.FlushW, .DCacheStallM, .SATP_REGW, .PCF,
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.FlushW, .DCacheStallW, .SATP_REGW, .PCF,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
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.ReadDataM(ReadDataM[`XLEN-1:0]), .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
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.IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
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@ -257,7 +257,7 @@ module lsu (
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.FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM),
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.ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
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.CacheWriteData(LSUWriteDataM), .SelHPTW,
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.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
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.CacheStall(DCacheStallW), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
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.CacheCommitted(DCacheCommittedM),
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.CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM),
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.FetchBuffer, .CacheBusRW,
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@ -296,14 +296,14 @@ module lsu (
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if(`DTIM_SUPPORTED) mux2 #(`XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM, SelDTIM, ReadDataWordMuxM);
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else assign ReadDataWordMuxM = FetchBuffer[`XLEN-1:0];
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assign LSUHBURST = 3'b0;
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assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
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assign {DCacheStallW, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
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end
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end else begin: nobus // block: bus
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assign LSUHWDATA = '0;
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assign ReadDataWordMuxM = DTIMReadDataWordM;
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assign {BusStall, BusCommittedM} = '0;
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assign {DCacheMiss, DCacheAccess} = '0;
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assign {DCacheStallM, DCacheCommittedM} = '0;
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assign {DCacheStallW, DCacheCommittedM} = '0;
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end
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/////////////////////////////////////////////////////////////////////////////////////////////
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@ -42,7 +42,7 @@ module hptw (
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] ReadDataM, // page table entry from LSU
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input logic [`XLEN-1:0] WriteDataM,
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input logic DCacheStallM, // stall from LSU
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input logic DCacheStallW, // stall from LSU
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input logic [2:0] Funct3M,
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input logic [6:0] Funct7M,
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input logic ITLBMissF,
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@ -117,7 +117,7 @@ module hptw (
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// State flops
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flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
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assign PRegEn = HPTWRW[1] & ~DCacheStallM | UpdatePTE;
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assign PRegEn = HPTWRW[1] & ~DCacheStallW | UpdatePTE;
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flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache
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@ -254,24 +254,24 @@ module hptw (
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IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState;
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else NextWalkerState = IDLE;
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L3_ADR: NextWalkerState = L3_RD; // first access in SV48
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L3_RD: if (DCacheStallM) NextWalkerState = L3_RD;
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L3_RD: if (DCacheStallW) NextWalkerState = L3_RD;
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else NextWalkerState = L2_ADR;
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L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // first access in SV39
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else NextWalkerState = LEAF;
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L2_RD: if (DCacheStallM) NextWalkerState = L2_RD;
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L2_RD: if (DCacheStallW) NextWalkerState = L2_RD;
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else NextWalkerState = L1_ADR;
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L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32
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else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
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else NextWalkerState = LEAF;
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L1_RD: if (DCacheStallM) NextWalkerState = L1_RD;
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L1_RD: if (DCacheStallW) NextWalkerState = L1_RD;
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else NextWalkerState = L0_ADR;
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L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD;
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else NextWalkerState = LEAF;
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L0_RD: if (DCacheStallM) NextWalkerState = L0_RD;
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L0_RD: if (DCacheStallW) NextWalkerState = L0_RD;
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else NextWalkerState = LEAF;
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LEAF: if (`HPTW_WRITES_SUPPORTED & DAPageFault) NextWalkerState = UPDATE_PTE;
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else NextWalkerState = IDLE;
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UPDATE_PTE: if(DCacheStallM) NextWalkerState = UPDATE_PTE;
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UPDATE_PTE: if(DCacheStallW) NextWalkerState = UPDATE_PTE;
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else NextWalkerState = LEAF;
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default: NextWalkerState = IDLE; // should never be reached
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endcase // case (WalkerState)
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||||
@ -306,5 +306,5 @@ module hptw (
|
||||
endmodule
|
||||
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||||
// another idea. We keep gating the control by ~FlushW, but this adds considerable length to the critical path.
|
||||
// should we do this differently? For example TLBMiss is gated by ~FlushW and then drives HPTWStall, which drives LSUStallM, which drives
|
||||
// should we do this differently? For example TLBMiss is gated by ~FlushW and then drives HPTWStall, which drives LSUStallW, which drives
|
||||
// the hazard unit to issue stall and flush controlls. ~FlushW already suppresses these in the hazard unit.
|
||||
|
||||
@ -119,8 +119,8 @@ module wallypipelinedcore (
|
||||
var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
|
||||
|
||||
// IMem stalls
|
||||
logic IFUStallF;
|
||||
logic LSUStallM;
|
||||
logic IFUStallD;
|
||||
logic LSUStallW;
|
||||
|
||||
|
||||
|
||||
@ -174,7 +174,7 @@ module wallypipelinedcore (
|
||||
.FlushD, .FlushE, .FlushM, .FlushW,
|
||||
// Fetch
|
||||
.HRDATA, .PCF, .IFUHADDR, .PCNext2F,
|
||||
.IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE,
|
||||
.IFUStallD, .IFUHBURST, .IFUHTRANS, .IFUHSIZE,
|
||||
.IFUHREADY, .IFUHWRITE,
|
||||
.ICacheAccess, .ICacheMiss,
|
||||
|
||||
@ -285,7 +285,7 @@ module wallypipelinedcore (
|
||||
.InstrDAPageFaultF,
|
||||
|
||||
.PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
|
||||
.LSUStallM); // change to LSUStallM
|
||||
.LSUStallW); // change to LSUStallW
|
||||
|
||||
|
||||
// *** Ross: please make EBU conditional when only supporting internal memories
|
||||
@ -319,7 +319,7 @@ module wallypipelinedcore (
|
||||
hazard hzu(
|
||||
.BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM,
|
||||
.LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
|
||||
.LSUStallM, .IFUStallF,
|
||||
.LSUStallW, .IFUStallD,
|
||||
.FCvtIntStallD, .FPUStallD,
|
||||
.DivBusyE, .FDivBusyE,
|
||||
.EcallFaultM, .BreakpointFaultM,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user