forked from Github_Repos/cvw
integrated tv generation for IFdivsqrt
This commit is contained in:
Alessandro Maiuolo
parent
f5c66b4464
commit
3990417d70
4
tests/fp/combined_IF_vectors/IF_vectors/README
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4
tests/fp/combined_IF_vectors/IF_vectors/README
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This folder holds the archtest and testfloat vectors necessary fo evaluating performance
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of standalone intdiv vs combined IFdivsqrt
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to generate vectors, uncomment line 8 in create_all_vectors.sh
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8
tests/fp/combined_IF_vectors/create_IF_vectors.sh
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8
tests/fp/combined_IF_vectors/create_IF_vectors.sh
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#!/bin/sh
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# create test vectors for stand alone int
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./extract_testfloat_vectors.py
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./extract_arch_vectors.py
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# to create tvs for evaluation of combined IFdivsqrt
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#./combined_IF_vectors/create_IF_vectors.sh
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251
tests/fp/combined_IF_vectors/extract_arch_vectors.py
Executable file
251
tests/fp/combined_IF_vectors/extract_arch_vectors.py
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#! /usr/bin/python3
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# author: Alessandro Maiuolo
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# contact: amaiuolo@g.hmc.edu
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# date created: 3-29-2023
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# extract all arch test vectors
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import os
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wally = os.popen('echo $WALLY').read().strip()
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def ext_bits(my_string):
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target_len = 32 # we want 128 bits, div by 4 bc hex notation
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zeroes_to_add = target_len - len(my_string)
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return zeroes_to_add*"0" + my_string
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def twos_comp(b, x):
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if b == 32:
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return hex(0x100000000 - int(x,16))[2:]
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elif b == 64:
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return hex(0x10000000000000000 - int(x,16))[2:]
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else:
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return "UNEXPECTED_BITSIZE"
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def unpack_rf(packed):
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bin_u = bin(int(packed, 16))[2:].zfill(8) # translate to binary
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flags = hex(int(bin_u[3:],2))[2:].zfill(2)
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rounding_mode = hex(int(bin_u[:3],2))[2:]
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return flags, rounding_mode
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# rounding mode dictionary
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round_dict = {
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"rne":"0",
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"rnm":"4",
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"ru":"3",
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"rz":"1",
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"rd":"2",
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"dyn":"7"
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}
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# fcsr dictionary
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fcsr_dict = {
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"0":"rne",
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"128":"rnm",
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"96":"ru",
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"32":"rz",
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"64":"rd",
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"224":"dyn"
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}
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print("creating arch test vectors")
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class Config:
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def __init__(self, bits, letter, op, filt, op_code):
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self.bits = bits
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self.letter = letter
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self.op = op
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self.filt = filt
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self.op_code = op_code
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def create_vectors(my_config):
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suite_folder_num = my_config.bits
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if my_config.bits == 64 and my_config.letter == "F": suite_folder_num = 32
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source_dir1 = "{}/addins/riscv-arch-test/riscv-test-suite/rv{}i_m/{}/src/".format(wally, suite_folder_num, my_config.letter)
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source_dir2 = "{}/tests/riscof/work/riscv-arch-test/rv{}i_m/{}/src/".format(wally, my_config.bits, my_config.letter)
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dest_dir = "{}/tests/fp/combined_IF_vectors/IF_vectors/".format(wally)
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all_vectors1 = os.listdir(source_dir1)
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filt_vectors1 = [v for v in all_vectors1 if my_config.filt in v]
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# print(filt_vectors1)
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filt_vectors2 = [v + "/ref/Reference-sail_c_simulator.signature" for v in all_vectors1 if my_config.filt in v]
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# iterate through all vectors
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for i in range(len(filt_vectors1)):
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vector1 = filt_vectors1[i]
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vector2 = filt_vectors2[i]
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operation = my_config.op_code
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rounding_mode = "X"
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flags = "XX"
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# use name to create our new tv
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dest_file = open("{}cvw_{}_{}.tv".format(dest_dir, my_config.bits, vector1[:-2]), 'a')
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# open vectors
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src_file1 = open(source_dir1 + vector1,'r')
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src_file2 = open(source_dir2 + vector2,'r')
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# for each test in the vector
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reading = True
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src_file2.readline() #skip first bc junk
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# print(my_config.bits, my_config.letter)
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if my_config.letter == "F" and my_config.bits == 64:
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reading = True
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# print("trigger 64F")
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#skip first 2 lines bc junk
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src_file2.readline()
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while reading:
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# get answer and flags from Ref...signature
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# answers are before deadbeef (first line of 4)
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# flags are after deadbeef (third line of 4)
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answer = src_file2.readline().strip()
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deadbeef = src_file2.readline().strip()
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# print(answer)
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if not (answer == "e7d4b281" and deadbeef == "6f5ca309"): # if there is still stuff to read
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# get flags
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packed = src_file2.readline().strip()[6:]
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flags, rounding_mode = unpack_rf(packed)
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# skip 00000000 buffer
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src_file2.readline()
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# parse through .S file
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detected = False
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done = False
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op1val = "0"
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op2val = "0"
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while not (detected or done):
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# print("det1")
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line = src_file1.readline()
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# print(line)
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if "op1val" in line:
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# print("det2")
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# parse line
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op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
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if my_config.op != "fsqrt": # sqrt doesn't have two input vals
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op2val = line.split("op2val")[1].split("x")[1].strip()
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if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
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else:
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op2val = 32*"X"
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# go to next test in vector
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detected = True
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elif "RVTEST_CODE_END" in line:
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done = True
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# put it all together
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if not done:
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translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()), flags, rounding_mode)
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dest_file.write(translation + "\n")
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else:
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# print("read false")
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reading = False
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elif my_config.letter == "M" and my_config.bits == 64:
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reading = True
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#skip first 2 lines bc junk
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src_file2.readline()
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while reading:
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# print("trigger 64M")
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# get answer from Ref...signature
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# answers span two lines and are reversed
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answer2 = src_file2.readline().strip()
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answer1 = src_file2.readline().strip()
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answer = answer1 + answer2
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# print(answer1,answer2)
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if not (answer2 == "e7d4b281" and answer1 == "6f5ca309"): # if there is still stuff to read
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# parse through .S file
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detected = False
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done = False
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op1val = "0"
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op2val = "0"
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while not (detected or done):
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# print("det1")
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line = src_file1.readline()
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# print(line)
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if "op1val" in line:
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# print("det2")
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# parse line
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op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
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if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
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op1val = twos_comp(my_config.bits, op1val)
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if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
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op2val = line.split("op2val")[1].split("x")[1].strip()
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if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
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if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
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op2val = twos_comp(my_config.bits, op2val)
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# go to next test in vector
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detected = True
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elif "RVTEST_CODE_END" in line:
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done = True
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# ints don't have flags
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flags = "XX"
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# put it all together
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if not done:
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translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()), flags.strip(), rounding_mode)
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dest_file.write(translation + "\n")
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else:
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# print("read false")
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reading = False
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else:
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while reading:
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# get answer and flags from Ref...signature
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answer = src_file2.readline()
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# print(answer)
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packed = src_file2.readline()[6:]
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# print(packed)
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if len(packed.strip())>0: # if there is still stuff to read
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# print("packed")
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# parse through .S file
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detected = False
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done = False
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op1val = "0"
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op2val = "0"
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while not (detected or done):
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# print("det1")
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line = src_file1.readline()
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# print(line)
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if "op1val" in line:
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# print("det2")
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# parse line
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op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
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if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
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op1val = twos_comp(my_config.bits, op1val)
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if my_config.op != "fsqrt": # sqrt doesn't have two input vals
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op2val = line.split("op2val")[1].split("x")[1].strip()
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if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
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if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
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op2val = twos_comp(my_config.bits, op2val)
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# go to next test in vector
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detected = True
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elif "RVTEST_CODE_END" in line:
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done = True
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# rounding mode for float
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if not done and (my_config.op == "fsqrt" or my_config.op == "fdiv"):
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flags, rounding_mode = unpack_rf(packed)
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# put it all together
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if not done:
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translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()), flags, rounding_mode)
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dest_file.write(translation + "\n")
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else:
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# print("read false")
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reading = False
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print("out")
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dest_file.close()
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src_file1.close()
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src_file2.close()
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config_list = [
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Config(32, "M", "div", "div_", 0),
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Config(32, "F", "fdiv", "fdiv", 1),
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Config(32, "F", "fsqrt", "fsqrt", 2),
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Config(32, "M", "rem", "rem-", 3),
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Config(32, "M", "divu", "divu-", 4),
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Config(32, "M", "remu", "remu-", 5),
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Config(64, "M", "div", "div-", 0),
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Config(64, "F", "fdiv", "fdiv", 1),
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Config(64, "F", "fsqrt", "fsqrt", 2),
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Config(64, "M", "rem", "rem-", 3),
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Config(64, "M", "divu", "divu-", 4),
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Config(64, "M", "remu", "remu-", 5),
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Config(64, "M", "divw", "divw-", 6),
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Config(64, "M", "divuw", "divuw-", 7),
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Config(64, "M", "remw", "remw-", 8),
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Config(64, "M", "remuw", "remuw-", 9)
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]
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for c in config_list:
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create_vectors(c)
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79
tests/fp/combined_IF_vectors/extract_testfloat_vectors.py
Executable file
79
tests/fp/combined_IF_vectors/extract_testfloat_vectors.py
Executable file
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#! /usr/bin/python3
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# extract sqrt and float div testfloat vectors
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# author: Alessandro Maiuolo
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# contact: amaiuolo@g.hmc.edu
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# date created: 3-29-2023
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import os
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wally = os.popen('echo $WALLY').read().strip()
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# print(wally)
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def ext_bits(my_string):
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target_len = 32 # we want 128 bits, div by 4 bc hex notation
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zeroes_to_add = target_len - len(my_string)
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return zeroes_to_add*"0" + my_string
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# rounding mode dictionary
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round_dict = {
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"rne":"0",
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"rnm":"4",
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"ru":"3",
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"rz":"1",
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"rd":"2",
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"dyn":"7"
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}
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print("creating testfloat div test vectors")
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source_dir = "{}/tests/fp/vectors/".format(wally)
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dest_dir = "{}/tests/fp/combined_IF_vectors/IF_vectors/".format(wally)
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all_vectors = os.listdir(source_dir)
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div_vectors = [v for v in all_vectors if "div" in v]
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# iterate through all float div vectors
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for vector in div_vectors:
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# use name to determine configs
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config_list = vector.split(".")[0].split("_")
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operation = "1" #float div
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rounding_mode = round_dict[str(config_list[2])]
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# use name to create our new tv
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dest_file = open(dest_dir + "cvw_" + vector, 'a')
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# open vector
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src_file = open(source_dir + vector,'r')
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# for each test in the vector
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for i in src_file.readlines():
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translation = "" # this stores the test that we are currently working on
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[input_1, input_2, answer, flags] = i.split("_") # separate inputs, answer, and flags
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# put it all together, strip nec for removing \n on the end of the flags
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translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(input_1), ext_bits(input_2), ext_bits(answer), flags.strip(), rounding_mode)
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dest_file.write(translation + "\n")
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dest_file.close()
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src_file.close()
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print("creating testfloat sqrt test vectors")
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sqrt_vectors = [v for v in all_vectors if "sqrt" in v]
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# iterate through all float div vectors
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for vector in sqrt_vectors:
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# use name to determine configs
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config_list = vector.split(".")[0].split("_")
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operation = "2" #sqrt
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rounding_mode = round_dict[str(config_list[2])]
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# use name to create our new tv
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dest_file = open(dest_dir + "cvw_" + vector, 'a')
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# open vector
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src_file = open(source_dir + vector,'r')
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# for each test in the vector
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for i in src_file.readlines():
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translation = "" # this stores the test that we are currently working on
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[input_1, answer, flags] = i.split("_") # separate inputs, answer, and flags
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# put it all together, strip nec for removing \n on the end of the flags
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translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(input_1), "X"*32, ext_bits(answer), flags.strip(), rounding_mode)
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dest_file.write(translation + "\n")
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dest_file.close()
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src_file.close()
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@ -3,3 +3,6 @@
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mkdir -p vectors
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./create_vectors.sh
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./remove_spaces.sh
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# to create tvs for evaluation of combined IFdivsqrt
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#./combined_IF_vectors/create_IF_vectors.sh
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Block a user