forked from Github_Repos/cvw
Added new PLIC and UART tests
This commit is contained in:
slmnemo
parent
49565f944c
commit
12c92a05ff
@ -0,0 +1,249 @@
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00000000 # read empty MIP (1.0.0)
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00000008 # check GPIO interrupt pending on intPending0
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00000000 # Claim gives no interrupt due to zero priority
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00000008 # interrupt still pending due to no claim
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00000000 # check no interrupts pending
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00000800 # MEIP set due to PLIC priority (1.0.1)
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00000008 # check GPIO interrupt pending on intPending0
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00000003 # claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending
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00000000 # check no interrupts pending
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00000000 # read empty MIP (1.0.2)
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00000000 # check GPIO interrupt pending on intPending0
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00000000 # claim gives no interrupt due to no intPending
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00000000 # no interrupts pending after clear
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00000000 # still no interrupts after clear
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00000000 # read empty MIP (1.1.0)
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00000008 # check GPIO interrupt pending on intPending0
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00000003 # Claim gives 3 for ID of GPIO
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00000000 # interrupt still pending due to no claim
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00000000 # check no interrupts pending
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00000800 # MEIP set due to PLIC priority (1.1.1)
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00000008 # check GPIO interrupt pending on intPending0
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00000003 # claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending after claim
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00000000 # check no interrupts pending
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00000000 # read empty MIP (1.2.0)
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00000008 # check GPIO interrupt pending on intPending0
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00000003 # Claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending after claim
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00000000 # check no interrupts pending
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00000800 # MEIP set due to PLIC priority (1.2.1)
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00000008 # check GPIO interrupt pending on intPending0
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00000003 # claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending after claim
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00000000 # check no interrupts pending
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00000000 # read empty MIP (1.3.0)
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00000008 # check GPIO interrupt pending on intPending0
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00000003 # Claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending after claim
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00000000 # check no interrupts pending
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00000800 # MEIP set due to PLIC priority (1.3.1)
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00000008 # check GPIO interrupt pending on intPending0
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00000003 # claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending after claim
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00000000 # check no interrupts pending
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00000000 # read empty MIP (1.4.0)
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00000008 # check GPIO interrupt pending on intPending0
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00000003 # Claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending after claim
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00000000 # check no interrupts pending
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00000800 # MEIP set due to PLIC priority (1.4.1)
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00000008 # check GPIO interrupt pending on intPending0
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00000003 # claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending after claim
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00000000 # check no interrupts pending
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00000000 # read empty MIP (1.5.0)
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00000008 # check GPIO interrupt pending on intPending0
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00000003 # Claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending after claim
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00000000 # check no interrupts pending
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00000800 # MEIP set due to PLIC priority (1.5.1)
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00000008 # check GPIO interrupt pending on intPending0
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00000003 # claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending after claim
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00000000 # check no interrupts pending
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00000000 # read empty MIP (1.6.0)
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00000008 # check GPIO interrupt pending on intPending0
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00000003 # Claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending after claim
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00000000 # check no interrupts pending
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00000800 # MEIP set due to PLIC priority (1.6.1)
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00000008 # check GPIO interrupt pending on intPending0
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00000003 # claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending after claim
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00000000 # check no interrupts pending
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00000000 # read empty MIP (1.7.0)
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00000008 # check GPIO interrupt pending on intPending0
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00000003 # Claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending after claim
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00000000 # check no interrupts pending
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00000800 # MEIP set (2.0)
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00000408 # gpio and uart pending
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00000003 # claim gpio
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00000400 # gpio no longer pending
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00000000 # no interrupts pending
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00000800 # MEIP set (2.1)
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00000408 # gpio and uart pending
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00000003 # claim gpio
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00000400 # gpio no longer pending
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00000000 # no interrupts pending
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00000800 # MEIP set (2.2)
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00000408 # gpio and uart pending
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0000000A # claim uart
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00000008 # uart no longer pending
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00000000 # no interrupts pending
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00000800 # MEIP set (2.3)
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00000408 # gpio and uart pending
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0000000A # claim uart
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00000008 # uart no longer pending
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00000000 # no interrupts pending
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00000000 # MEIP empty (2.4)
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00000408 # gpio and uart pending
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0000000A # claim none
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00000008 # gpio and uart still pending
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00000000 # no interrupts pending
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00000A00 # MEIP and SEIP set (3.0)
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00000408 # check GPIO and UART interrupt pending on intPending0
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00000003 # claim gives 3 for ID of GPIO
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00000400 # check GPIO interrupt pending cleared after claim
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00000000 # check no interrupts pending
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00000200 # SEIP set (3.1)
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00000408 # check GPIO and UART interrupt pending on intPending0
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00000003 # claim gives 3 for ID of GPIO
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00000400 # check GPIO interrupt pending cleared after claim
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00000000 # check no interrupts pending
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00000200 # SEIP set (3.2)
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00000408 # check GPIO and UART interrupt pending on intPending0
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0000000A # claim UART
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00000008 # GPIO interrupt pending after UART claimcomp
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00000000 # check no interrupts pending
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00000000 # read empty MIP (3.3)
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00000408 # check GPIO and UART interrupt pending on intPending0
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0000000A # claim UART
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00000008 # check UART interrupt pending cleared after claim
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00000000 # check no interrupts pending
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00000A00 # MEIP and SEIP set (4.0)
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00000400 # UART interrupt pending
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0000000A # claim UART
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00000000 # check no interrupts pending
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00000000 # check no interrupts pending
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00000200 # SEIP set (4.1)
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00000400 # UART interrupt pending
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00000000 # nothing in claim register
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00000400 # UART interrupt pending
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00000000 # check no interrupts pending
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00000A00 # MEIP and SEIP set (4.2)
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00000400 # UART interrupt pending
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0000000A # claim UART
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00000000 # check no interrupts pending
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00000000 # check no interrupts pending
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00000800 # MEIP set (4.3)
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00000400 # UART interrupt pending
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0000000A # claim UART
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00000000 # check no interrupts pending
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00000000 # check no interrupts pending
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00000800 # MEIP set (4.4)
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00000400 # UART interrupt pending
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0000000A # claim UART
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00000000 # check no interrupts pending
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00000000 # check no interrupts pending
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00000200 # SEIP set (4.5)
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00000400 # UART interrupt pending
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00000000 # nothing in claim register
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00000400 # UART interrupt pending
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00000000 # check no interrupts pending
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00000000 # All disabled (4.6)
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00000400 # UART interrupt pending
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00000000 # nothing in claim register
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00000400 # UART interrupt pending
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00000000 # check no interrupts pending
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00000200 # SEIP set (5.0)
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00000008 # GPIO interrupt pending
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00000000 # nothing in claim register
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00000008 # GPIO interrupt pending
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00000000 # check no interrupts pending
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00000A00 # MEIP and SEIP set (5.1)
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00000008 # GPIO interrupt pending
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00000003 # claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending
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00000000 # check no interrupts pending
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00000800 # MEIP set (5.2)
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00000008 # GPIO interrupt pending
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00000003 # claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending
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00000000 # check no interrupts pending
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00000A00 # MEIP and SEIP set (5.3)
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00000008 # GPIO interrupt pending
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00000003 # claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending
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00000000 # check no interrupts pending
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00000800 # MEIP set (5.4)
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00000008 # GPIO interrupt pending
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00000003 # claim gives 3 for ID of GPIO
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00000000 # check no interrupts pending
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00000000 # check no interrupts pending
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00000200 # SEIP set (5.5)
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00000008 # GPIO interrupt pending
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00000000 # nothing in claim register
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00000008 # GPIO interrupt pending
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00000000 # check no interrupts pending
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00000000 # read empty MIP (5.6)
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00000008 # GPIO interrupt pending
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00000000 # nothing in claim register
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00000008 # GPIO interrupt pending
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00000000 # check no interrupts pending
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0000000b # written due to goto_s_mode
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00000200 # read sip (7.0)
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00000408 # check GPIO and UART interrupt pending on intPending0
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00000003 # claim gives 3 for ID of GPIO
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00000400 # check GPIO interrupt pending cleared after claim
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00000000 # check no interrupts pending
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00000200 # read sip (7.1)
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00000408 # check GPIO and UART interrupt pending on intPending0
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00000003 # claim gives 3 for ID of GPIO
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00000400 # check GPIO interrupt pending cleared after claim
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00000000 # check no interrupts pending
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00000200 # read sip (7.2)
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00000408 # check GPIO and UART interrupt pending on intPending0
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0000000A # claim UART
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00000008 # GPIO interrupt pending after UART claimcomp
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00000000 # check no interrupts pending
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00000200 # read sip (7.3)
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00000408 # check GPIO and UART interrupt pending on intPending0
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00000003 # claim gives 3 for ID of GPIO
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00000400 # check GPIO interrupt pending cleared after claim
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00000000 # check no interrupts pending
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00000000 # read sip
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00000408 # check GPIO and UART interrupt pending on intPending0
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00000000 # nothing in claim register
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00000408 # check GPIO and UART interrupt pending on intPending0
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00000000 # check no interrupts pending
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00000200 # read sip
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00000408 # check GPIO and UART interrupt pending on intPending0
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00000003 # claim gives 3 for ID of GPIO
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00000400 # check GPIO interrupt pending cleared after claim
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00000000 # check no interrupts pending
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00000000 # read sip
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00000408 # check GPIO and UART interrupt pending on intPending0
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00000000 # nothing in claim register
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00000408 # check GPIO and UART interrupt pending on intPending0
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00000000 # check no interrupts pending
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00000009 # output from ecall in supervisor mode
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00000800 # MEIP set
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00000408 # check GPIO and UART interrupt pending on intPending0
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0000000A # claim UART
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00000008 # GPIO interrupt pending after UART claimcomp
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00000003 # claim gives 3 for ID of GPIO
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00000000 # read empty MIP # no interrupts, meip is low
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00000000 # check no interrupts pending
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00000800 # MEIP set
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00000008 # GPIO interrupt pending after complete
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00000003 # claim gives 3 for ID of GPIO
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00000000 # read empty MIP # meip is zeroed
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00000000 # check no interrupts pending
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00000800 # MEIP set
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00000400 # check GPIO interrupt pending cleared after claim
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00000800 # MEIP set
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00000408 # check GPIO and UART interrupt pending on intPending0
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0000000A # claim UART
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@ -0,0 +1,33 @@
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00000000 # Reset tests
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00000001 # 00000000 *** commented because LCR should reset to zero but resets to 3 due to the FPGA
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00000000
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00000060
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00000000
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00000060 # read-write test
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00000020 # transmitter register empty but shift register not
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00000101 # transmitter is not empty when done transmitting 5 bits
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00000000
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00000060
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00000101 # Multi-bit transmission: 5 bits
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00000015
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00000101 # Transmit 6 bits
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0000002A
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00000101 # Transmit 7 bits
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0000007F
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00000101 # Transmit 8 bits
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00000080
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00000002 # Transmission interrupt tests
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00000401 # Interrupt generated by finished transmission
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00000004
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00000006 # IIR return LSR intr and LSR has an overflow error
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00000063
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00000004
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00000001
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00000001 # MODEM interrupt tests
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00000000
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00000011
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00000001
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0000000b # ecall from test termination
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@ -0,0 +1,951 @@
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///////////////////////////////////////////
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//
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// WALLY-plic
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//
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// Author: David_Harris@hmc.edu and Nicholas Lucio <nlucio@hmc.edu>
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//
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// Created 2022-06-16
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#include "WALLY-TEST-LIB-32.h"
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INIT_TESTS
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TRAP_HANDLER m
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j run_test_loop // begin test loop/table tests instead of executing inline code.
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INIT_TEST_TABLE
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END_TESTS
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TEST_STACK_AND_DATA
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.align 2
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test_cases:
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# ---------------------------------------------------------------------------------------------
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# Test Contents
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#
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# Here is where the actual tests are held, or rather, what the actual tests do.
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# each entry consists of 3 values that will be read in as follows:
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#
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# '.4byte [x28 Value], [x29 Value], [x30 value]'
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# or
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# '.4byte [address], [value], [test type]'
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#
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# The encoding for x30 test type values can be found in the test handler in the framework file
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#
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# ---------------------------------------------------------------------------------------------
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# =========== Define PLIC registers ===========
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.equ PLIC, 0x0C000000
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.equ PLIC_INTPRI_GPIO, (PLIC+0x00000C) # GPIO is interrupt 3
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.equ PLIC_INTPRI_UART, (PLIC+0x000028) # UART is interrupt 10
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.equ PLIC_INTPENDING0, (PLIC+0x001000) # intPending0 register
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.equ PLIC_INTEN00, (PLIC+0x002000) # interrupt enables for context 0 (machine mode) sources 31:1
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.equ PLIC_INTEN10, (PLIC+0x002080) # interrupt enables for context 1 (supervisor mode) sources 31:1
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.equ PLIC_THRESH0, (PLIC+0x200000) # Priority threshold for context 0 (machine mode)
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.equ PLIC_CLAIM0, (PLIC+0x200004) # Claim/Complete register for context 0
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.equ PLIC_THRESH1, (PLIC+0x201000) # Priority threshold for context 1 (supervisor mode)
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.equ PLIC_CLAIM1, (PLIC+0x201004) # Claim/Complete register for context 1
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# =========== Define GPIO registers ===========
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.equ GPIO, 0x10060000
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.equ input_val, (GPIO+0x00)
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.equ input_en, (GPIO+0x04)
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.equ output_en, (GPIO+0x08)
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.equ output_val, (GPIO+0x0C)
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.equ rise_ie, (GPIO+0x18)
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.equ rise_ip, (GPIO+0x1C)
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.equ fall_ie, (GPIO+0x20)
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.equ fall_ip, (GPIO+0x24)
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.equ high_ie, (GPIO+0x28)
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.equ high_ip, (GPIO+0x2C)
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.equ low_ie, (GPIO+0x30)
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.equ low_ip, (GPIO+0x34)
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.equ iof_en, (GPIO+0x38)
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.equ iof_sel, (GPIO+0x3C)
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.equ out_xor, (GPIO+0x40)
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# =========== Define UART registers ===========
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.equ UART, 0x10000000
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.equ UART_IER, (UART+0x01)
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.equ UART_MCR, (UART+0x04)
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.equ UART_MSR, (UART+0x06)
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# =========== Initialize UART and GPIO ===========
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# GPIO Initialization
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.4byte input_en, 0x00000001, write32_test # enable bit 0 of input_en
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.4byte output_en, 0x00000001, write32_test # enable bit 0 of output_en
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.4byte output_val, 0x00000000, write32_test # make sure output_val is 0
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.4byte rise_ie, 0x00000001, write32_test # enable rise interrupts
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# =========== Initialize relevant PLIC registers ===========
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.4byte PLIC_INTPRI_GPIO, 0x00000000, write32_test # set GPIO priority to zero
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.4byte PLIC_INTPRI_UART, 0x00000000, write32_test # set UART priority to zero
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.4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
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.4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
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.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
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.4byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max
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# =========== Machine-Mode Priority Testing (1.T.X) ===========
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# Test 1.0.0: GPIO int lacks priority (0 = 0)
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.4byte PLIC_THRESH0, 0x00000000, write32_test # change threshold
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.0.1: GPIO int has priority (1 > 0)
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.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # let GPIO cause interrupts
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.0.2: meip and c/c clear without interrupt pending
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
|
||||
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
|
||||
# Test 1.1.0: GPIO lacks priority (1 = 1)
|
||||
.4byte PLIC_THRESH0, 0x00000001, write32_test # change threshold
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
|
||||
# Test 1.1.1: GPIO int has priority (2 > 1)
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # let GPIO cause interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
|
||||
# Test 1.2.0: GPIO int lacks priority (2 = 2)
|
||||
.4byte PLIC_THRESH0, 0x00000002, write32_test # change threshold
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
|
||||
# Test 1.2.1: GPIO int has priority (3 > 2)
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # let GPIO cause interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
|
||||
# Test 1.3.0: GPIO int lacks priority (3 = 3)
|
||||
.4byte PLIC_THRESH0, 0x00000003, write32_test # change threshold
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
|
||||
# Test 1.3.1: GPIO int has priority (4 > 3)
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # let GPIO cause interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
|
||||
# Test 1.4.0: GPIO int lacks priority (4 = 4)
|
||||
.4byte PLIC_THRESH0, 0x00000004, write32_test # change threshold
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
|
||||
# Test 1.4.1: GPIO int has priority (5 > 4)
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000005, write32_test # let GPIO cause interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
|
||||
# Test 1.5.0: GPIO int lacks priority (5 = 5)
|
||||
.4byte PLIC_THRESH0, 0x00000005, write32_test # change threshold
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
|
||||
# Test 1.5.1: GPIO int has priority (6 > 5)
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # let GPIO cause interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
|
||||
# Test 1.6.0: GPIO int lacks priority (6 = 6)
|
||||
.4byte PLIC_THRESH0, 0x00000006, write32_test # change threshold
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
|
||||
# Test 1.6.1: GPIO int has priority (7 > 6)
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000007, write32_test # let GPIO cause interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
|
||||
# Test 1.7.0: GPIO int lacks priority (7 = 7)
|
||||
.4byte PLIC_THRESH0, 0x00000007, write32_test # change threshold
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
|
||||
# =========== UART vs GPIO priority (2.X) ===========
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
|
||||
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
||||
.4byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max
|
||||
# UART Initialization
|
||||
.4byte UART_IER, 0x08, write08_test # enable modem status interrupts from CTS
|
||||
.4byte UART_MCR, 0x10, write08_test # enable loopback mode, RTS = 0
|
||||
.4byte UART_MSR, 0x00, write08_test # disable UART interrupt
|
||||
|
||||
# Test 2.0: GPIO Priority = UART Priority
|
||||
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1
|
||||
.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UARTPriority = 1
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 2.1: GPIO Priority > UART Priority
|
||||
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # GPIOPriority = 3
|
||||
.4byte PLIC_INTPRI_UART, 0x00000002, write32_test # UARTPriority = 2
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 2.2: GPIO Priority < UART Priority
|
||||
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # GPIOPriority = 4
|
||||
.4byte PLIC_INTPRI_UART, 0x00000005, write32_test # UARTPriority = 5
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for UART
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 2.3: GPIO Priority < UART Priority
|
||||
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIOPriority = 6
|
||||
.4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UARTPriority = 7
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for UART
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 2.4: Interrupts don't have enough priority
|
||||
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # GPIOPriority = 4
|
||||
.4byte PLIC_INTPRI_UART, 0x00000005, write32_test # UARTPriority = 5
|
||||
.4byte PLIC_THRESH0, 0x00000006, write32_test # set m-mode threshold to 6
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# =========== SEIP tests (3.X) ===========
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
|
||||
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
||||
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
||||
|
||||
# Test 3.0: Cause machine and supervisor interrupts
|
||||
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1
|
||||
.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UARTPriority = 1
|
||||
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
||||
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000A00, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 3.1: Suppress machine mode interrupts
|
||||
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # GPIOPriority = 3
|
||||
.4byte PLIC_INTPRI_UART, 0x00000002, write32_test # UARTPriority = 2
|
||||
.4byte PLIC_THRESH0, 0x00000007, write32_test # set m-mode threshold to 7
|
||||
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000200, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 3.2: Cause SEIP with UART first
|
||||
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIOPriority = 6
|
||||
.4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UARTPriority = 7
|
||||
.4byte PLIC_THRESH0, 0x00000007, write32_test # set m-mode threshold to 7
|
||||
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000200, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 3.3: Low SEIP due to insufficient priority
|
||||
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # GPIOPriority = 2
|
||||
.4byte PLIC_INTPRI_UART, 0x00000003, write32_test # UARTPriority = 3
|
||||
.4byte PLIC_THRESH0, 0x00000004, write32_test # set m-mode threshold to 4
|
||||
.4byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 5
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# =========== UART interrupt enable tests (4.X) ===========
|
||||
|
||||
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
||||
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1
|
||||
.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1
|
||||
|
||||
# Test 4.0: GPIO m-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000A00, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 4.1: UART m-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000200, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 4.2: GPIO s-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000A00, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 4.3: UART s-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 4.4: GPIO and UART s-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 4.5: GPIO and UART m-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000200, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 4.6: GPIO and UART fully disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000200, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# =========== GPIO interrupt enable tests (5.X) ===========
|
||||
|
||||
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
||||
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1
|
||||
.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1
|
||||
|
||||
# Test 5.0: GPIO m-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte 0x0, 0x00000200, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 5.1: UART m-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte 0x0, 0x00000A00, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 5.2: GPIO s-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 5.3: UART s-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte 0x0, 0x00000A00, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 5.4: GPIO and UART s-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 5.5: GPIO and UART m-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte 0x0, 0x00000200, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 5.6: GPIO and UART fully disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# =========== S-mode enable tests (7.X) ===========
|
||||
|
||||
.4byte 0x0, 0x0, goto_s_mode # go to s-mode. 0xb written to output
|
||||
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
||||
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1
|
||||
.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1
|
||||
|
||||
# Test 7.0: GPIO m-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000200, readsip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 7.1: UART m-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000200, readsip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 7.2: GPIO s-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000200, readsip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM1, 0x0000000A, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM1, 0x0000000A, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 7.3: UART s-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000200, readsip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 7.4: GPIO and UART s-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000000, readsip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM1, 0x00000000, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 7.5: GPIO and UART m-mode disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000200, readsip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# Test 7.6: GPIO and UART fully disabled
|
||||
|
||||
.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000000, readsip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
.4byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
.4byte PLIC_CLAIM1, 0x00000000, write32_test # complete claim made earlier
|
||||
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
|
||||
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
# =========== Special claim tests (8) ===========
|
||||
|
||||
.4byte 0x0, 0x0, goto_m_mode # write 0x9 to output
|
||||
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIO Priority = 6
|
||||
.4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UART Priority = 7
|
||||
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
|
||||
.4byte PLIC_THRESH0, 0x00000005, write32_test # set m-mode threshold to 5
|
||||
|
||||
# Test 8
|
||||
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # read interrupt pending
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # claim UART
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # UART interrupt cleared
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # claim GPIO
|
||||
.4byte 0x0, 0x00000000, readmip_test # no interrupts, meip is low
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # both interrupts claimed
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete GPIO
|
||||
.4byte 0x0, 0x00000800, readmip_test # GPIO interrupt sets MEIP
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # GPIO bit is set
|
||||
.4byte PLIC_CLAIM0, 0x00000003, read32_test # claim GPIO again
|
||||
.4byte 0x0, 0x00000000, readmip_test # meip is zeroed
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # both interrupts claimed
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete UART claim
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # UART pending
|
||||
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete GPIO claim
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # GPIO and UART pending
|
||||
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # claim UART
|
||||
|
||||
.4byte 0x0, 0x0, terminate_test # terminate tests
|
||||
@ -0,0 +1,493 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-gpio
|
||||
//
|
||||
// Author: David_Harris@hmc.edu and Nicholas Lucio <nlucio@hmc.edu>
|
||||
//
|
||||
// Created 2022-06-16
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
TRAP_HANDLER m
|
||||
|
||||
j run_test_loop // begin test loop/table tests instead of executing inline code.
|
||||
|
||||
INIT_TEST_TABLE
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
|
||||
.align 2
|
||||
test_cases:
|
||||
# ---------------------------------------------------------------------------------------------
|
||||
# Test Contents
|
||||
#
|
||||
# Here is where the actual tests are held, or rather, what the actual tests do.
|
||||
# each entry consists of 3 values that will be read in as follows:
|
||||
#
|
||||
# '.4byte [x28 Value], [x29 Value], [x30 value]'
|
||||
# or
|
||||
# '.4byte [address], [value], [test type]'
|
||||
#
|
||||
# The encoding for x30 test type values can be found in the test handler in the framework file
|
||||
#
|
||||
# ---------------------------------------------------------------------------------------------
|
||||
|
||||
# =========== Define PLIC registers ===========
|
||||
|
||||
.equ PLIC, 0x0C000000
|
||||
.equ PLIC_INTPRI_GPIO, (PLIC+0x00000C) # GPIO is interrupt 3
|
||||
.equ PLIC_INTPRI_UART, (PLIC+0x000028) # UART is interrupt 10
|
||||
.equ PLIC_INTPENDING0, (PLIC+0x001000) # intPending0 register
|
||||
.equ PLIC_INTEN00, (PLIC+0x002000) # interrupt enables for context 0 (machine mode) sources 31:1
|
||||
.equ PLIC_INTEN10, (PLIC+0x002080) # interrupt enables for context 1 (supervisor mode) sources 31:1
|
||||
.equ PLIC_THRESH0, (PLIC+0x200000) # Priority threshold for context 0 (machine mode)
|
||||
.equ PLIC_CLAIM0, (PLIC+0x200004) # Claim/Complete register for context 0
|
||||
.equ PLIC_THRESH1, (PLIC+0x201000) # Priority threshold for context 1 (supervisor mode)
|
||||
.equ PLIC_CLAIM1, (PLIC+0x201004) # Claim/Complete register for context 1
|
||||
|
||||
# =========== Define GPIO registers ===========
|
||||
|
||||
.equ GPIO, 0x10060000
|
||||
.equ input_val, (GPIO+0x00)
|
||||
.equ input_en, (GPIO+0x04)
|
||||
.equ output_en, (GPIO+0x08)
|
||||
.equ output_val, (GPIO+0x0C)
|
||||
.equ rise_ie, (GPIO+0x18)
|
||||
.equ rise_ip, (GPIO+0x1C)
|
||||
.equ fall_ie, (GPIO+0x20)
|
||||
.equ fall_ip, (GPIO+0x24)
|
||||
.equ high_ie, (GPIO+0x28)
|
||||
.equ high_ip, (GPIO+0x2C)
|
||||
.equ low_ie, (GPIO+0x30)
|
||||
.equ low_ip, (GPIO+0x34)
|
||||
.equ iof_en, (GPIO+0x38)
|
||||
.equ iof_sel, (GPIO+0x3C)
|
||||
.equ out_xor, (GPIO+0x40)
|
||||
|
||||
# =========== Define UART registers ===========
|
||||
|
||||
.equ UART, 0x10000000
|
||||
.equ UART_IER, (UART+0x01)
|
||||
.equ UART_MCR, (UART+0x04)
|
||||
.equ UART_MSR, (UART+0x06)
|
||||
|
||||
# =========== Initialize UART and GPIO ===========
|
||||
|
||||
# GPIO Initialization
|
||||
.4byte input_en, 0x00000001, write32_test # enable bit 0 of input_en
|
||||
.4byte output_en, 0x00000001, write32_test # enable bit 0 of output_en
|
||||
.4byte output_val, 0x00000000, write32_test # make sure output_val is 0
|
||||
.4byte rise_ie, 0x00000001, write32_test # enable rise interrupts
|
||||
|
||||
# UART Initialization
|
||||
.4byte UART_IER, 0x08, write08_test # enable modem status interrupts from CTS
|
||||
.4byte UART_MCR, 0x10, write08_test # enable loopback mode, RTS = 0
|
||||
.4byte UART_MSR, 0x00, write08_test # disable UART interrupt
|
||||
|
||||
# =========== Initialize relevant PLIC registers ===========
|
||||
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000000, write32_test # set GPIO priority to zero
|
||||
.4byte PLIC_INTPRI_UART, 0x00000000, write32_test # set UART priority to zero
|
||||
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
|
||||
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
|
||||
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
||||
.4byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max
|
||||
|
||||
# =========== Machine-Mode Priority Testing (1.T.X) ===========
|
||||
|
||||
# Test 1.0.0: GPIO int lacks priority (0 = 0)
|
||||
.4byte PLIC_THRESH0, 0x00000000, write32_test # change threshold
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect no interrupt pending *** pending bug?????
|
||||
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
|
||||
# Test 1.0.1: GPIO int has priority (1 > 0)
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # let GPIO cause interrupts
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
|
||||
# Test 1.0.2: meip and c/c clear without interrupt pending
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
|
||||
|
||||
# Test 1.1.0: GPIO lacks priority (1 = 1)
|
||||
.4byte PLIC_THRESH0, 0x00000001, write32_test # change threshold
|
||||
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
|
||||
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
|
||||
# Test 1.1.1: GPIO int has priority (2 > 1)
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # let GPIO cause interrupts
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
|
||||
# Test 1.2.0: GPIO int lacks priority (2 = 2)
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte PLIC_THRESH0, 0x00000002, write32_test # change threshold
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
|
||||
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
|
||||
# Test 1.2.1: GPIO int has priority (3 > 2)
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # let GPIO cause interrupts
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
|
||||
# Test 1.3.0: GPIO int lacks priority (3 = 3)
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte PLIC_THRESH0, 0x00000003, write32_test # change threshold
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
|
||||
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
|
||||
# Test 1.3.1: GPIO int has priority (4 > 3)
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # let GPIO cause interrupts
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
|
||||
# Test 1.4.0: GPIO int lacks priority (4 = 4)
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte PLIC_THRESH0, 0x00000004, write32_test # change threshold
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
|
||||
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
|
||||
# Test 1.4.1: GPIO int has priority (5 > 4)
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000005, write32_test # let GPIO cause interrupts
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
|
||||
# Test 1.5.0: GPIO int lacks priority (5 = 5)
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte PLIC_THRESH0, 0x00000005, write32_test # change threshold
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
|
||||
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
|
||||
# Test 1.5.1: GPIO int has priority (6 > 5)
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # let GPIO cause interrupts
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
|
||||
# Test 1.6.0: GPIO int lacks priority (6 = 6)
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte PLIC_THRESH0, 0x00000006, write32_test # change threshold
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
|
||||
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
|
||||
# Test 1.6.1: GPIO int has priority (7 > 6)
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte PLIC_INTPRI_GPIO, 0x00000007, write32_test # let GPIO cause interrupts
|
||||
.4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
|
||||
.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
|
||||
# Test 1.7.0: GPIO int lacks priority (7 = 7)
|
||||
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
|
||||
.4byte PLIC_THRESH0, 0x00000007, write32_test # change threshold
|
||||
.4byte 0x0, 0x00000000, readmip_test # read mip
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
|
||||
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
|
||||
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
|
||||
.4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
|
||||
|
||||
# # =========== UART vs GPIO priority (2.X) =========== ***
|
||||
|
||||
# .4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
|
||||
# .4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
|
||||
# .4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
||||
# .4byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max
|
||||
|
||||
# # Test 2.0: GPIO Priority = UART Priority
|
||||
|
||||
# .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UARTPriority = 1
|
||||
# .4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # GPIO claim/complete process
|
||||
# .4byte PLIC_INTPENDING0, 0x00000200, read32_test # GPIO interrupt was cleared
|
||||
# .4byte 0x0, 0x00000800, readmip_test # expect mip to remain high
|
||||
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # UART claim/complete process
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # UART interrupt pending was cleared
|
||||
# .4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
|
||||
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
|
||||
# # Test 2.1: GPIO Priority < UART Priority
|
||||
|
||||
# .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # GPIO Priority = 2
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000003, write32_test # UART Priority = 3
|
||||
# .4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for UART and GPIO
|
||||
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # UART claim/complete process
|
||||
# .4byte PLIC_INTPENDING0, 0x00000008, read32_test # UART interrupt was cleared
|
||||
# .4byte 0x0, 0x00000800, readmip_test # expect mip to remain high
|
||||
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # GPIO claim/complete process
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # GPIO interrupt pending was cleared
|
||||
# .4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
|
||||
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
|
||||
# # Test 2.2: GPIO Priority > UART Priority
|
||||
|
||||
# .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000005, write32_test # GPIO Priority = 5
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000004, write32_test # UART Priority = 4
|
||||
# .4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # GPIO claim/complete process
|
||||
# .4byte PLIC_INTPENDING0, 0x00000200, read32_test # GPIO interrupt was cleared
|
||||
# .4byte 0x0, 0x00000800, readmip_test # expect mip to remain high
|
||||
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # UART claim/complete process
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # UART interrupt pending was cleared
|
||||
# .4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
|
||||
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
|
||||
# # Test 2.3: GPIO Priority < UART Priority (2)
|
||||
|
||||
# .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIO Priority = 6
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UART Priority = 7
|
||||
# .4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for UART and GPIO
|
||||
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # UART claim/complete process
|
||||
# .4byte PLIC_INTPENDING0, 0x00000008, read32_test # UART interrupt was cleared
|
||||
# .4byte 0x0, 0x00000800, readmip_test # expect mip to remain high
|
||||
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # GPIO claim/complete process
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # GPIO interrupt pending was cleared
|
||||
# .4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
|
||||
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
|
||||
# # Test 2.4: Interrupts disabled (Thresh0 = 7)
|
||||
|
||||
# .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_THRESH0, 0x00000007, write32_test # Disable m-mode interrupts
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000007, write32_test # GPIO Priority = 7
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UART Priority = 7
|
||||
# .4byte 0x0, 0x00000000, readmip_test, # read mip
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
# .4byte 0x0, 0x00000000, readmclaimcomplete_test # no interrupt pending
|
||||
# .4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
|
||||
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
|
||||
# # =========== SEIP tests (3.X) ===========
|
||||
|
||||
# .4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
|
||||
# .4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
|
||||
# .4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
||||
# .4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
||||
|
||||
# # Test 3.0: Cause machine and supervisor interrupts
|
||||
|
||||
# .4byte output_val, 0x00000000, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1
|
||||
# .4byte 0x0, 0x00000A00, readmip_test # Expect high on MEIP and SEIP
|
||||
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # Expect GPIO on claim/complete
|
||||
# .4byte 0x0, 0x00000A00, readmip_test # Still expect high on MEIP and SEIP
|
||||
# .4byte PLIC_INTPENDING0, 0x00000200, read32_test # GPIO interrupt was cleared
|
||||
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # Expect UART on claim/complete
|
||||
# .4byte 0x0, 0x00000000, readmip_test # all interrupts were cleared
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # Pending should also be clear
|
||||
# .4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
|
||||
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
|
||||
# # Test 3.1: Suppress machine mode interrupts
|
||||
|
||||
# .4byte output_val, 0x00000000, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # GPIO Priority = 3
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000002, write32_test # UART Priority = 2
|
||||
# .4byte PLIC_THRESH0, 0x00000007, write32_test # set m-mode threshold to 7
|
||||
# .4byte 0x0, 0x00000200, readmip_test # Expect high on SEIP only
|
||||
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # Expect GPIO on claim/complete
|
||||
# .4byte 0x0, 0x00000200, readmip_test # Expect high on SEIP only
|
||||
# .4byte PLIC_INTPENDING0, 0x00000200, read32_test # GPIO interrupt was cleared
|
||||
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # Expect UART on claim/complete
|
||||
# .4byte 0x0, 0x00000000, readmip_test # all interrupts were cleared
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # Pending should also be clear
|
||||
# .4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
|
||||
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
|
||||
# # Test 3.2: Cause SEIP with UART first
|
||||
|
||||
# .4byte output_val, 0x00000000, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIO Priority = 6
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UART Priority = 7
|
||||
# .4byte 0x0, 0x00000200, readmip_test # Expect high on SEIP only
|
||||
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # Expect UART on claim/complete
|
||||
# .4byte 0x0, 0x00000200, readmip_test # Expect high on SEIP only
|
||||
# .4byte PLIC_INTPENDING0, 0x00000008, read32_test # UART interrupt was cleared
|
||||
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # Expect GPIO on claim/complete
|
||||
# .4byte 0x0, 0x00000000, readmip_test # all interrupts were cleared
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # Pending should also be clear
|
||||
# .4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
|
||||
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
|
||||
# # Test 3.3: Low SEIP due to insufficient priority
|
||||
|
||||
# .4byte output_val, 0x00000000, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # GPIO Priority = 2
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000003, write32_test # UART Priority = 3
|
||||
# .4byte PLIC_THRESH0, 0x00000004, write32_test # set m-mode threshold to 7
|
||||
# .4byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 7
|
||||
# .4byte 0x0, 0x00000000, readmip_test # no interrupt pending
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
# .4byte 0x0, 0x00000000, readmclaimcomplete_test # Expect nothing on claim/complete
|
||||
# .4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
|
||||
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
|
||||
# # =========== UART interrupt enable tests (4.X) ===========
|
||||
|
||||
# .4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
||||
# .4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1
|
||||
|
||||
# # Test 4.0: GPIO m-mode disabled
|
||||
|
||||
# .4byte output_val, 0x00000000, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_INTEN00, 0x000000200, write32_test # GPIO m-mode interrupt disabled
|
||||
# .4byte PLIC_INTEN00, 0x000000208, write32_test # No s-mode interrupt disabled
|
||||
# .4byte 0x0, 0x00000A00, readmip_test # Expect high on MEIP from UART and SEIP from GPIO
|
||||
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # Expect GPIO on claim/complete
|
||||
# .4byte 0x0, 0x00000200, readmip_test # Expect high on MEIP and SEIP from UART
|
||||
# .4byte PLIC_INTPENDING0, 0x00000200, read32_test # interrupt pending for GPIO and UART
|
||||
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # Expect UART on claim/complete
|
||||
# .4byte 0x0, 0x00000000, readmip_test # all interrupts were cleared
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # Pending should also be clear
|
||||
|
||||
# Test 4.1: UART m-mode disabled
|
||||
|
||||
|
||||
|
||||
# Test 4.2: GPIO s-mode disabled
|
||||
|
||||
|
||||
|
||||
# Test 4.3: UART s-mode disabled
|
||||
|
||||
|
||||
|
||||
# Test 4.4: GPIO and UART s-mode disabled
|
||||
|
||||
|
||||
|
||||
# Test 4.5: GPIO and UART m-mode disabled
|
||||
|
||||
|
||||
|
||||
# Test 4.6: GPIO and UART fully disabled
|
||||
|
||||
.4byte 0x0, 0x0, terminate_test # terminate tests
|
||||
@ -0,0 +1,140 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-uart
|
||||
//
|
||||
// Author: David_Harris@hmc.edu and Nicholas Lucio <nlucio@hmc.edu>
|
||||
//
|
||||
// Created 2022-06-16
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
TRAP_HANDLER m
|
||||
|
||||
j run_test_loop // begin test loop/table tests instead of executing inline code.
|
||||
|
||||
INIT_TEST_TABLE
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
|
||||
.align 2
|
||||
|
||||
.equ UART, 0x10000000
|
||||
.equ UART_RBR, (UART)
|
||||
.equ UART_THR, (UART)
|
||||
.equ UART_IER, (UART+0x01)
|
||||
.equ UART_IIR, (UART+0x02)
|
||||
.equ UART_FCR, (UART+0x02)
|
||||
.equ UART_LCR, (UART+0x03)
|
||||
.equ UART_MCR, (UART+0x04)
|
||||
.equ UART_LSR, (UART+0x05)
|
||||
.equ UART_MSR, (UART+0x06)
|
||||
.equ UART_Scr, (UART+0x07)
|
||||
|
||||
test_cases:
|
||||
# ---------------------------------------------------------------------------------------------
|
||||
# Test Contents
|
||||
#
|
||||
# Here is where the actual tests are held, or rather, what the actual tests do.
|
||||
# each entry consists of 3 values that will be read in as follows:
|
||||
#
|
||||
# '.4byte [x28 Value], [x29 Value], [x30 value]'
|
||||
# or
|
||||
# '.4byte [address], [value], [test type]'
|
||||
#
|
||||
# The encoding for x30 test type values can be found in the test handler in the framework file
|
||||
#
|
||||
# ---------------------------------------------------------------------------------------------
|
||||
|
||||
# =========== UART resets to correct values on master reset ===========
|
||||
|
||||
.4byte UART_IER, 0x00, read08_test
|
||||
.4byte UART_IIR, 0x01, read08_test # IIR resets to 1
|
||||
# .4byte UART_LCR, 0x00, read08_test *** commented out because LCR should reset to zero but resets to 3
|
||||
.4byte UART_MCR, 0x00, read08_test
|
||||
.4byte UART_LSR, 0x60, read08_test # LSR resets with transmit status bits set
|
||||
.4byte UART_MSR, 0x00, read04_test
|
||||
|
||||
# =========== Basic read-write ===========
|
||||
|
||||
.4byte UART_LCR, 0x00, write08_test # set LCR to reset value *** remove if UART resets to correct value
|
||||
.4byte UART_MCR, 0x10, write08_test # put UART into loopback for MSR test
|
||||
.4byte UART_LSR, 0x60, read08_test
|
||||
.4byte UART_THR, 0x00, write08_test # write value to UART
|
||||
.4byte UART_LSR, 0x00, read08_test # data not ready and transmitter is not empty
|
||||
.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and LSR
|
||||
.4byte UART_RBR, 0x00, read08_test # read written value
|
||||
.4byte UART_LSR, 0x60, read08_test # read LSR
|
||||
|
||||
# =========== Different size read-write ===========
|
||||
|
||||
# Transmit 5 bits
|
||||
|
||||
.4byte UART_LCR, 0x00, write08_test # set LCR to transmit 5 bits
|
||||
.4byte UART_THR, 0x55, write08_test # write value to UART
|
||||
.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR
|
||||
.4byte UART_RBR, 0x15, read08_test # read written value without bits 5-7
|
||||
|
||||
# Transmit 6 bits
|
||||
|
||||
.4byte UART_LCR, 0x01, write08_test # set LCR to transmit six bits
|
||||
.4byte UART_THR, 0xAA, write08_test # write value to UART
|
||||
.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR
|
||||
.4byte UART_RBR, 0x2A, read08_test # read written value without bits 6 & 7
|
||||
|
||||
# Transmit 7 bits
|
||||
|
||||
.4byte UART_LCR, 0x02, write08_test # set LCR to transmit seven bits
|
||||
.4byte UART_THR, 0xFF, write08_test # write value to UART
|
||||
.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR
|
||||
.4byte UART_RBR, 0x7F, read08_test # read written value without bit 7
|
||||
|
||||
# Transmit 8 bits
|
||||
|
||||
.4byte UART_LCR, 0x03, write08_test # set LCR to transmit seven bits
|
||||
.4byte UART_THR, 0x80, write08_test # write value to UART
|
||||
.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR
|
||||
.4byte UART_RBR, 0x80, read08_test # read full written value + sign extension
|
||||
|
||||
# =========== Transmit-related interrupts ===========
|
||||
|
||||
.4byte UART_IER, 0x07, write08_test # enable data available, buffer empty, and line status interrupts
|
||||
.4byte UART_IIR, 0x02, read08_test # buffer should be empty, causing interrupt
|
||||
.4byte UART_THR, 0x00, write08_test # write zeroes to transmitter
|
||||
.4byte 0x0, 0x0401, uart_data_wait # IIR should have data ready interrupt
|
||||
.4byte UART_THR, 0x01, write08_test # write 1 to transmitter buffer
|
||||
.4byte UART_IIR, 0x04, read08_test # data interrupt should still be high
|
||||
.4byte 0x0, 0x06, uart_lsr_intr_wait # wait for transmission to complete, IIR should throw error due to overrun error.
|
||||
.4byte UART_LSR, 0x63, read08_test # read overrun error from LSR
|
||||
.4byte UART_IIR, 0x04, read08_test # check that LSR interrupt was cleared
|
||||
.4byte UART_RBR, 0x01, read08_test # read previous value from UART
|
||||
|
||||
# =========== MODEM interrupts ===========
|
||||
|
||||
.4byte UART_MSR, 0x00, write08_test # clear MSR
|
||||
.4byte UART_IER, 0x08, write08_test # enable MODEM Status interrupts
|
||||
.4byte UART_IIR, 0x01, read08_test # no interrupts pending
|
||||
.4byte UART_MCR, 0x02, write08_test # Cause DCTS interrupt
|
||||
.4byte UART_IIR, 0x00, read08_test # MODEM interrupt
|
||||
.4byte UART_MSR, 0x11, read08_test # Read MSR to clear interrupt
|
||||
.4byte UART_IIR, 0x01, read08_test # interrupt cleared by reading MSR
|
||||
|
||||
.4byte 0x0, 0x0, terminate_test
|
||||
Loading…
Reference in New Issue
Block a user