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modified testbench.sv- now works with coremark

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DTowersM 2022-06-07 23:58:50 +00:00
parent c46fbf2260
commit 02a424d65b
2 changed files with 5 additions and 5 deletions
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3
benchmarks/riscv-coremark/Makefile
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@ -11,9 +11,6 @@ work/coremark.bare.riscv.elf.memfile: work/coremark.bare.riscv
riscv64-unknown-elf-elf2hex --bit-width 64 --input $< --output $@
extractFunctionRadix.sh $<.elf.objdump
work/coremark.bare.riscv.objdump: work/coremark.bare.riscv
riscv64-unknown-elf-objdump -D work/coremark.bare.riscv > work/coremark.bare.riscv.objdump
work/coremark.bare.riscv: $(sources) Makefile
# make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/opt/riscv/riscv-gnu-toolchain XCFLAGS="-march=rv64imd -mabi=lp64d -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-7-series -Ofast -funroll-all-loops -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 -funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fno-toplevel-reorder --param=max-inline-insns-size=128 -fipa-pta"
# These flags were used by WD on CoreMark

7
pipelined/testbench/testbench.sv
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@ -162,8 +162,8 @@ logic [3:0] dummy;
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
// initialize tests
localparam integer MemStartAddr = `RAM_BASE>>(1+`XLEN/32);
localparam integer MemEndAddr = (`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32);
localparam integer MemStartAddr = 0;
localparam integer MemEndAddr = `RAM_RANGE>>1+(`XLEN/32);
initial
begin
@ -204,6 +204,9 @@ logic [3:0] dummy;
// if ($time % 100000 == 0) $display("Time is %0t", $time);
end
logic [`XLEN-1:0] debugmemoryadr;
assign debugmemoryadr = dut.uncore.ram.ram.memory.RAM[5140];
// check results
always @(negedge clk)
begin