forked from Github_Repos/cvw
Simplified integer division preprocessing in fdivsqrt
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@ -61,7 +61,7 @@ module fdivsqrtpreproc (
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if (`IDIV_ON_FPU) begin:intpreproc // Int Supported
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logic signedDiv, NegQuotE;
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logic AsBit, BsBit, AsE, BsE, ALTBE;
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logic AsE, BsE, ALTBE;
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logic [`XLEN-1:0] AE, BE, PosA, PosB;
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logic [`DIVBLEN:0] ZeroDiff, p;
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@ -71,22 +71,16 @@ module fdivsqrtpreproc (
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// Source handling
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if (`XLEN==64) begin // 64-bit, supports W64
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mux2 #(1) azeromux(~(|ForwardedSrcAE), ~(|ForwardedSrcAE[31:0]), W64E, AZeroE);
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mux2 #(1) bzeromux(~(|ForwardedSrcBE), ~(|ForwardedSrcBE[31:0]), W64E, BZeroE);
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mux2 #(1) abitmux(ForwardedSrcAE[63], ForwardedSrcAE[31], W64E, AsBit);
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mux2 #(1) bbitmux(ForwardedSrcBE[63], ForwardedSrcBE[31], W64E, BsBit);
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mux2 #(64) amux(ForwardedSrcAE, {{(`XLEN-32){AsE}}, ForwardedSrcAE[31:0]}, W64E, AE);
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mux2 #(64) bmux(ForwardedSrcBE, {{(`XLEN-32){BsE}}, ForwardedSrcBE[31:0]}, W64E, BE);
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assign AsE = signedDiv & AsBit;
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assign BsE = signedDiv & BsBit;
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mux2 #(64) amux(ForwardedSrcAE, {{32{ForwardedSrcAE[31] & signedDiv}}, ForwardedSrcAE[31:0]}, W64E, AE);
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mux2 #(64) bmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31] & signedDiv}}, ForwardedSrcBE[31:0]}, W64E, BE);
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end else begin // 32 bits only
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assign AsE = signedDiv & ForwardedSrcAE[31];
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assign BsE = signedDiv & ForwardedSrcBE[31];
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assign AE = ForwardedSrcAE;
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assign BE = ForwardedSrcBE;
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assign AZeroE = ~(|ForwardedSrcAE);
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assign BZeroE = ~(|ForwardedSrcBE);
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end
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end
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assign AZeroE = ~(|AE);
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assign BZeroE = ~(|BE);
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assign AsE = AE[`XLEN-1] & signedDiv;
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assign BsE = BE[`XLEN-1] & signedDiv;
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// Force integer inputs to be postiive
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mux2 #(`XLEN) posamux(AE, -AE, AsE, PosA);
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