fpu idiv working on all configs with 1 copy of radix 2!

pipelined/config/buildroot/wally-config.vh

@@ -72,7 +72,7 @@
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 `define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 0
+`define IDIV_ON_FPU 1
 
 // Legal number of PMP entries are 0, 16, or 64
 `define PMP_ENTRIES 16

pipelined/config/fpga/wally-config.vh

@@ -74,7 +74,7 @@
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 `define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 0
+`define IDIV_ON_FPU 1
 
 // Legal number of PMP entries are 0, 16, or 64
 `define PMP_ENTRIES 64

pipelined/config/rv32e/wally-config.vh

@@ -73,7 +73,7 @@
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 `define IDIV_BITSPERCYCLE 1
-`define IDIV_ON_FPU 0
+`define IDIV_ON_FPU 1
 
 // Legal number of PMP entries are 0, 16, or 64
 `define PMP_ENTRIES 0

pipelined/config/rv32gc/wally-config.vh

@@ -72,7 +72,7 @@
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 `define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 0
+`define IDIV_ON_FPU 1
 
 // Legal number of PMP entries are 0, 16, or 64
 `define PMP_ENTRIES 64

pipelined/config/rv32i/wally-config.vh

@@ -73,7 +73,7 @@
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 `define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 0
+`define IDIV_ON_FPU 1
 
 // Legal number of PMP entries are 0, 16, or 64
 `define PMP_ENTRIES 64

pipelined/config/rv32ic/wally-config.vh

@@ -72,7 +72,7 @@
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 `define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 0
+`define IDIV_ON_FPU 1
 
 // Legal number of PMP entries are 0, 16, or 64
 `define PMP_ENTRIES 0

pipelined/config/rv64BP/wally-config.vh

@@ -76,7 +76,7 @@
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 `define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 0
+`define IDIV_ON_FPU 1
 
 // Address space
 `define RESET_VECTOR 64'h0000000000001000

pipelined/config/rv64fpquad/wally-config.vh

@@ -74,7 +74,7 @@
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 `define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 0
+`define IDIV_ON_FPU 1
 
 // Legal number of PMP entries are 0, 16, or 64
 `define PMP_ENTRIES 64

pipelined/config/rv64gc/wally-config.vh

@@ -74,7 +74,7 @@
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 `define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 0
+`define IDIV_ON_FPU 1
 
 // Legal number of PMP entries are 0, 16, or 64
 `define PMP_ENTRIES 64

pipelined/config/rv64i/wally-config.vh

@@ -74,7 +74,7 @@
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 `define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 0
+`define IDIV_ON_FPU 1
 
 // Legal number of PMP entries are 0, 16, or 64
 `define PMP_ENTRIES 0

pipelined/src/fpu/fdivsqrt/fdivsqrt.sv

@@ -66,13 +66,13 @@ module fdivsqrt(
   logic WZeroE, AZeroM, BZeroM, AZeroE, BZeroE;
   logic SpecialCaseM, MDUM;
   logic [`DIVBLEN:0] nE, nM, mM;
-  logic NegQuotM, ALTBM, AsM;
+  logic NegQuotM, ALTBM, AsM, W64M;
   logic DivStartE;
   logic [`XLEN-1:0] ForwardedSrcAM;
 
   fdivsqrtpreproc fdivsqrtpreproc(
     .clk, .IFDivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), 
-    .Sqrt(SqrtE), .Ym(YmE), .XZeroE, .X, .DPreproc, .ForwardedSrcAM, .MDUM,
+    .Sqrt(SqrtE), .Ym(YmE), .XZeroE, .X, .DPreproc, .ForwardedSrcAM, .MDUM, .W64M,
     .nE, .nM, .mM, .NegQuotM, .ALTBM, .AZeroM, .BZeroM, .AZeroE, .BZeroE, .AsM,
     .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .MDUE, .W64E);
   fdivsqrtfsm fdivsqrtfsm(
@@ -89,6 +89,6 @@ module fdivsqrt(
     .clk, .reset, .StallM,
     .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .MDUE, .Firstun, 
     .SqrtM, .SpecialCaseM, .RemOpM(Funct3M[1]), .ForwardedSrcAM,
-    .nM, .ALTBM, .mM, .BZeroM, .AsM, .NegQuotM,
+    .nM, .ALTBM, .mM, .BZeroM, .AsM, .NegQuotM, .W64M,
     .QmM, .WZeroE, .DivSM, .FPIntDivResultM);
 endmodule

pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -40,7 +40,7 @@ module fdivsqrtpostproc(
   input  logic              SqrtE, MDUE,
   input  logic              Firstun, SqrtM, SpecialCaseM, NegQuotM,
 	input  logic [`XLEN-1:0]  ForwardedSrcAM,
-  input  logic              RemOpM, ALTBM, BZeroM, AsM, 
+  input  logic              RemOpM, ALTBM, BZeroM, AsM, W64M,
   input  logic [`DIVBLEN:0] nM, mM,
   output logic [`DIVb:0]    QmM, 
   output logic              WZeroE,
@@ -51,12 +51,12 @@ module fdivsqrtpostproc(
   logic [`DIVb+3:0] W, Sum, DM;
   logic [`DIVb:0] PreQmM;
   logic NegStickyM;
-  logic weq0E, weq0M;
+  logic weq0E, weq0M, WZeroM;
   logic [`DIVBLEN:0] NormShiftM;
   logic [`DIVb:0] NormQuotM;
   logic [`DIVb+3:0] IntQuotM, IntRemM, NormRemM;
   logic signed [`DIVb+3:0] PreResultM, PreFPIntDivResultM;
-  logic WZeroM;
+  logic [`XLEN-1:0] W64FPIntDivResultM;
 
   //////////////////////////
   // Execute Stage: Detect early termination for an exact result
@@ -166,7 +166,8 @@ module fdivsqrtpostproc(
    // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
   
   assign PreFPIntDivResultM = $signed(PreResultM >>> NormShiftM);
-  assign FPIntDivResultM = BZeroM ? (RemOpM ? ForwardedSrcAM : {(`XLEN){1'b1}}) : PreFPIntDivResultM[`XLEN-1:0]; // special cases
+  assign W64FPIntDivResultM = (W64M ? {{(`XLEN-32){PreFPIntDivResultM[31]}}, PreFPIntDivResultM[31:0]} : PreFPIntDivResultM[`XLEN-1:0]); // Sign extending in case of W64
+  assign FPIntDivResultM = BZeroM ? (RemOpM ? ForwardedSrcAM : {(`XLEN){1'b1}}) : W64FPIntDivResultM; // special cases
  
   assign PreQmM = NegStickyM ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit
   assign QmM = SqrtM ? (PreQmM << 1) : PreQmM;

pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -42,7 +42,7 @@ module fdivsqrtpreproc (
 	input  logic [2:0] 	Funct3E,
 	input  logic MDUE, W64E,
   output logic [`DIVBLEN:0] nE, nM, mM,
-  output logic NegQuotM, ALTBM, MDUM,
+  output logic NegQuotM, ALTBM, MDUM, W64M,
   output logic AsM, AZeroM, BZeroM, AZeroE, BZeroE,
   output logic [`NE+1:0] QeM,
   output logic [`DIVb+3:0] X,
@@ -58,7 +58,7 @@ module fdivsqrtpreproc (
   logic  [`DIVb-1:0] IFNormLenX, IFNormLenD;
   logic  [`XLEN-1:0] PosA, PosB;
   logic  AsE, BsE, ALTBE, NegQuotE;
-  logic  [`XLEN-1:0]  A64, B64;
+  logic  [`XLEN-1:0]  A64, B64, A64Src;
   logic  [`DIVBLEN:0] mE;
   logic  [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;
   logic  [`DIVBLEN:0] pPlusr, pPrCeil, p, ell;
@@ -69,17 +69,18 @@ module fdivsqrtpreproc (
   // ***can probably merge X LZC with conversion
   // cout the number of leading zeros
 
-  assign AsE = ForwardedSrcAE[`XLEN-1] & ~Funct3E[0];
-  assign BsE = ForwardedSrcBE[`XLEN-1] & ~Funct3E[0];
+  assign AsE = ~Funct3E[0] & (W64E ? ForwardedSrcAE[31] : ForwardedSrcAE[`XLEN-1]);
+  assign BsE = ~Funct3E[0] & (W64E ? ForwardedSrcBE[31] : ForwardedSrcBE[`XLEN-1]);
   assign A64 = W64E ? {{(`XLEN-32){AsE}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE;
   assign B64 = W64E ? {{(`XLEN-32){BsE}}, ForwardedSrcBE[31:0]} : ForwardedSrcBE;
+  assign A64Src = W64E ? {{(`XLEN-32){ForwardedSrcAE[31]}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE;
 
   assign NegQuotE = (AsE ^ BsE) & MDUE;
   
   assign PosA = AsE ? -A64 : A64;
   assign PosB = BsE ? -B64 : B64;
-  assign AZeroE = ~(|ForwardedSrcAE);
-  assign BZeroE = ~(|ForwardedSrcBE);
+  assign AZeroE = W64E ? ~(|ForwardedSrcAE[31:0]) : ~(|ForwardedSrcAE);
+  assign BZeroE = W64E ? ~(|ForwardedSrcBE[31:0]) : ~(|ForwardedSrcBE);
 
   assign IFNormLenX = MDUE ? {PosA, {(`DIVb-`XLEN){1'b0}}} : {Xm, {(`DIVb-`NF-1){1'b0}}};
   assign IFNormLenD = MDUE ? {PosB, {(`DIVb-`XLEN){1'b0}}} : {Ym, {(`DIVb-`NF-1){1'b0}}};
@@ -126,16 +127,17 @@ module fdivsqrtpreproc (
   // r = 1 or 2
   // DIVRESLEN/(r*`DIVCOPIES)
 
-  flopen #(`NE+2)    expreg(clk, IFDivStartE, QeE, QeM);
   flopen #(1)    negquotreg(clk, IFDivStartE, NegQuotE, NegQuotM);
   flopen #(1)       altbreg(clk, IFDivStartE, ALTBE, ALTBM);
   flopen #(1)      azeroreg(clk, IFDivStartE, AZeroE, AZeroM);
   flopen #(1)      bzeroreg(clk, IFDivStartE, BZeroE, BZeroM);
   flopen #(1)      asignreg(clk, IFDivStartE, AsE, AsM);
   flopen #(1)        mdureg(clk, IFDivStartE, MDUE, MDUM);
+  flopen #(1)        w64reg(clk, IFDivStartE, W64E, W64M);
   flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM);
   flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
-  flopen #(`XLEN)   srcareg(clk, IFDivStartE, ForwardedSrcAE, ForwardedSrcAM);
+  flopen #(`NE+2)    expreg(clk, IFDivStartE, QeE, QeM);
+  flopen #(`XLEN)   srcareg(clk, IFDivStartE, A64Src, ForwardedSrcAM);
 
 
 endmodule