forked from Github_Repos/cvw
divsqrt comment cleanup
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@ -62,7 +62,7 @@ module fdivsqrtfsm(
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if (reset) begin
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state <= #1 IDLE;
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end else if (DivStart&~StallE) begin
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step <= (`DURLEN)'(`FPDUR); // *** this should be adjusted to depend on the precision
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step <= (`DURLEN)'(`FPDUR); // *** this should be adjusted to depend on the precision; sqrt should use one fewer step becasue firststep=1
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if (SpecialCase) state <= #1 DONE;
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else state <= #1 BUSY;
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end else if (DivDone) begin
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@ -94,7 +94,7 @@ module fdivsqrtiter(
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assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+2:0], 1'b0};
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assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+2:0], 1'b0};
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assign NextC = {1'b1, C[`DIVCOPIES-1][`DIVb-1:1]};
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end else begin
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end else begin : nextw
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assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+1:0], 2'b0};
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assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+1:0], 2'b0};
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assign NextC = {2'b11, C[`DIVCOPIES-1][`DIVb-1:2]};
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@ -102,6 +102,7 @@ module fdivsqrtiter(
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if (`RADIX == 2) assign initC = {1'b1, {(`DIVb-1){1'b0}}}; // *** note that these are preshifted right by r compared to book
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else assign initC = {2'b11, {(`DIVb-2){1'b0}}};
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// assign initC = 0;
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// mux2 #(`DIVb+4) wsmux(NextWSN, {3'b0, X}, DivStart, WSN);
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mux2 #(`DIVb+4) wsmux(NextWSN, {{3{SqrtE&~XZeroE}}, X}, DivStart, WSN);
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@ -130,7 +131,7 @@ module fdivsqrtiter(
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.C(C[i]), .S(S[i]), .SM(SM[i]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i]));
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end else begin: stage
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logic j1;
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assign j1 = (i == 0 & C[0][`DIVb-2] & ~C[0][`DIVb-3]); // not quite right ***
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assign j1 = (i == 0 & C[0][`DIVb-2] & ~C[0][`DIVb-3]);
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fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM, .j1,
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.WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]),
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.C(C[i]), .S(S[i]), .SM(SM[i]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i]));
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@ -159,6 +160,7 @@ module fdivsqrtiter(
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mux2 #(`DIVb+1) QMmux(QMNext[`DIVCOPIES-1], '1, DivStart, QMMux);
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flopen #(`DIVb+1) QMreg(clk, DivStart|DivBusy, QMMux, QM[0]);
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// if starting new square root, set S to 1 and SM to 0
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flopenr #(`DIVb+1) SMreg(clk, DivStart, DivBusy, SMNext[`DIVCOPIES-1], SM[0]);
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mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], {1'b1, {(`DIVb){1'b0}}}, DivStart, SMux);
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flopen #(`DIVb+1) Sreg(clk, DivStart|DivBusy, SMux, S[0]);
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