Added comments in fcvt

pipelined/src/fpu/fcvtfp.sv

@@ -30,11 +30,17 @@ module cvtfp (
     logic [31:0] DSRes; // double to single precision result
 
 
+    // add support for all formats
+    // consider reordering code blocks so upconverting is in one region of the file
+    // and downconverting is in the other region.
 
     ///////////////////////////////////////////////////////////////////////////////
-    // LZC
+    // LZC: Leading Zero Counter
     ///////////////////////////////////////////////////////////////////////////////
 
+    // *** consider sharing this with fcvtint
+    // *** emphasize parallel structure between the two
+    // *** add a priorityencoder module to generic (similar to priorityonehot) and use it
 
     // LZC - find the first 1 in the input's mantissa
 	logic [8:0]	i,NormCnt;

pipelined/src/fpu/fcvtint.sv

@@ -61,6 +61,10 @@ module fcvt (
       //  fcvt.d.l  = 100
       //  fcvt.d.lu = 110
       //  {long, unsigned, to int}
+
+    // *** revisit this module, explain in more depth
+    // should the int to fp and fp to int paths be separated?
+    // add support for all formats
    
     // calculate signals based off the input and output's size
     assign Res64 = (FOpCtrlE[0]&FOpCtrlE[2]) | (FmtE&~FOpCtrlE[0]);