Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix MISA RO and UART addresses

Browse Source 
It appears on inspection that the MISA register is read only in Wally
In which case this has now also been set in the ImperasDV representation
Also the Addresss for the UART R/W privileges are corrected
This commit is contained in:
eroom1966 2023-03-13 11:07:19 +00:00
parent 23f6d58247
commit 0d260accb4
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
sim/imperas.ic
View File

@ -6,6 +6,7 @@
--override cpu/ignore_non_leaf_DAU=1
--override cpu/wfi_is_nop=T
--override cpu/mimpid=0x100
--override cpu/misa_Extensions_mask=0x0
# THIS NEEDS FIXING to 16
--override cpu/PMP_registers=0

3
testbench/testbench_imperas.sv
View File

@ -178,8 +178,7 @@ module testbench;
void'(rvviRefMemorySetVolatile(`GPIO_BASE, (`GPIO_BASE + `GPIO_RANGE)));
end
if (`UART_SUPPORTED) begin
//void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + `UART_RANGE)));
void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + 7))); // BUG
void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + `UART_RANGE)));
end
if (`PLIC_SUPPORTED) begin
void'(rvviRefMemorySetVolatile(`PLIC_BASE, (`PLIC_BASE + `PLIC_RANGE)));