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Added line to testbench to prevent annoying burst sizes

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slmnemo 2022-05-25 17:29:45 -07:00
parent cebf93cf9c
commit d1421b88ad
1 changed files with 1 additions and 0 deletions
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pipelined/testbench/testbench.sv
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@ -374,6 +374,7 @@ module riscvassertions;
//assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS.");
//assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS.");
assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
end
endmodule