Merge pull request #24 from ross144/main

Added comments to serveral files to cleanup code.

gitflow.txt

@@ -9,7 +9,7 @@
 ## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
 ## may obtain a copy of the License at
 ##
-## https:##solderpad.org/licenses/SHL-2.1/
+## https://solderpad.org/licenses/SHL-2.1/
 ##
 ## Unless required by applicable law or agreed to in writing, any work distributed under the 
 ## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
@@ -29,10 +29,17 @@ Once per sessiosn
 
 Fetch upstream and sync fork
 1. git fetch upstream
-2. git push
+2. git merge upstream/main
 
 Create pull request
-1. gh pr create
-2. Must include a title and strongly encourage a body message explaining your changes.
-3. Wait for pull request to be approved, rejected, or needs changes.
-4. Finish by fetching the upstream and pushing back to your fork.
+1. git fetch upstream
+2. git merge upstream/main
+3. git push
+4. gh pr create
+5. Must include a title and strongly encourage a body message explaining your changes.
+6. Wait for pull request to be approved, rejected, or needs changes.
+7. Finish by fetching the upstream and pushing back to your fork.
+   1. git fetch upstream
+   2. git merge upstream/main
+   3. git push
+        

pipelined/src/lsu/lrsc.sv

@@ -31,21 +31,23 @@
 `include "wally-config.vh"
 
 module lrsc(
-  input  logic                clk, reset,
+  input  logic                clk, 
+  input  logic                reset,
   input  logic                StallW,
-  input  logic                MemReadM,
-  input  logic [1:0]          PreLSURWM,
-  output logic [1:0]          LSURWM,
-  input  logic [1:0] 	        LSUAtomicM,
-  input  logic [`PA_BITS-1:0] PAdrM,  // from mmu to dcache
-  output logic                SquashSCW
+  input  logic                MemReadM,   // Memory read
+  input  logic [1:0]          PreLSURWM,  // Memory operation from the HPTW or IEU [1]: read, [0]: write
+  output logic [1:0]          LSURWM,     // Memory operation after potential squash of SC
+  input  logic [1:0] 	      LSUAtomicM, // Atomic memory operaiton
+  input  logic [`PA_BITS-1:0] PAdrM,      // Physical memory address 
+  output logic                SquashSCW   // Squash the store conditional by not allowing rf write
 );
 
+  // possible bug: *** double check if PreLSURWM needs to be flushed by ignorerequest.
   // Handle atomic load reserved / store conditional
-  logic [`PA_BITS-1:2] 			  ReservationPAdrW;
-  logic 						          ReservationValidM, ReservationValidW; 
-  logic 						          lrM, scM, WriteAdrMatchM;
-  logic 						          SquashSCM;
+  logic [`PA_BITS-1:2] 		  ReservationPAdrW;
+  logic 					  ReservationValidM, ReservationValidW; 
+  logic 					  lrM, scM, WriteAdrMatchM;
+  logic 					  SquashSCM;
 
   assign lrM = MemReadM & LSUAtomicM[0];
   assign scM = PreLSURWM[0] & LSUAtomicM[0]; 

pipelined/src/lsu/lsu.sv

@@ -32,8 +32,8 @@
 `include "wally-config.vh"
 
 module lsu (
-  input  logic                clk,set,
-  input  logic                StallM,ushM, StallW, FlushW,
+  input  logic                clk, reset,
+  input  logic                StallM, FlushM, StallW, FlushW,
   output logic                LSUStallM,                            // LSU stalls pipeline during a multicycle operation
   // connected to cpu (controls)
   input  logic [1:0]          MemRWM,                               // Read/Write control
@@ -58,7 +58,7 @@ module lsu (
   input  logic [`FLEN-1:0]    FWriteDataM,                          // Write data from FPU
   input  logic                FpLoadStoreM,                         // Selects FPU as store for write data
   // faults
-  output logic                LoadPageFaultM,oreAmoPageFaultM,      // Page fault exceptions
+  output logic                LoadPageFaultM, StoreAmoPageFaultM,   // Page fault exceptions
   output logic                LoadMisalignedFaultM,                 // Load address misaligned fault
   output logic                LoadAccessFaultM,                     // Load access fault (PMA)
   output logic                HPTWInstrAccessFaultM,                // HPTW generated access fault during instruction fetch
@@ -77,7 +77,7 @@ module lsu (
   output logic [`XLEN/8-1:0]  LSUHWSTRB,                            // Bus byte write enables from LSU to EBU
   // page table walker
   input  logic [`XLEN-1:0]    SATP_REGW,                            // SATP (supervisor address translation and protection) CSR
-  input  logic                STATUS_MXR,ATUS_SUM, STATUS_MPRV,     // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
+  input  logic                STATUS_MXR, STATUS_SUM, STATUS_MPRV,     // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
   input  logic [1:0]          STATUS_MPP,                           // Machine previous privilege mode
   input  logic [`XLEN-1:0]    PCF,                                  // Fetch PC 
   input  logic                ITLBMissF,                            // ITLB miss causes HPTW (hardware pagetable walker) walk
@@ -86,7 +86,7 @@ module lsu (
   output logic [1:0]          PageType,                             // Type of page table entry to write to ITLB
   output logic                ITLBWriteF,                           // Write PTE to ITLB
   output logic                SelHPTW,                              // During a HPTW walk the effective privilege mode becomes S_MODE
-  input var logic [7:0]       PMPCFG_ARRAY_REGW[P_ENTRIES-1:0],     // PMP configuration from privileged unit
+  input var logic [7:0]       PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],     // PMP configuration from privileged unit
   input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]  // PMP address from privileged unit
 );