1955 Commits

Author	SHA1	Message	Date
Ross Thompson	6e7e318396	Fixed bug in the LSU pagetable walker interlock.	2021-07-06 10:41:36 -05:00
David Harris	b4082ba776	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-06 10:44:17 -04:00
David Harris	30fdd7abc8	Cleaned up tlb output muxing	2021-07-06 10:44:05 -04:00
David Harris	d58cad89a8	Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines	2021-07-06 10:38:30 -04:00
Kip Macsai-Goren	7e9961cac4	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-06 10:16:34 -04:00
David Harris	694badcc6b	Created tlbcontrol module to hide details	2021-07-06 03:25:11 -04:00
David Harris	f805aea236	Implemented TSR, TW, TVM, MXR status bits	2021-07-06 01:32:05 -04:00
David Harris	8b23162d6d	Fixed adrdecs to use Access signals for TIMs	2021-07-05 23:42:58 -04:00
David Harris	71711c54c9	Don't generate HPTW when MEM_VIRTMEM=0	2021-07-05 23:35:44 -04:00
David Harris	179c8d3ed4	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-05 23:23:17 -04:00
David Harris	6bac566bb7	Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0	2021-07-05 20:35:31 -04:00
Ross Thompson	530ddd667b	Fixed combo loop in the page table walker.	2021-07-05 16:37:26 -05:00
Ross Thompson	2a62ee2e70	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-05 16:07:27 -05:00
Kip Macsai-Goren	20cd0e208b	added new mmu tests to makefrag and commented out in the testbench	2021-07-05 10:54:30 -04:00
David Harris	5f91b339aa	Added F_SUPPORTED flag to disable floating point unit when not in MISA	2021-07-05 10:30:46 -04:00
David Harris	ac163e091c	Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported	2021-07-04 19:33:46 -04:00
David Harris	004cac91e1	Simplified PLIC with generate	2021-07-04 19:17:15 -04:00
David Harris	0aae58abed	Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb	2021-07-04 19:02:56 -04:00
David Harris	600e7802dd	Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb	2021-07-04 18:56:30 -04:00
David Harris	db5a06beaf	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-04 18:55:24 -04:00
David Harris	b23192cf1b	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
bbracker	287935c09d	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-04 18:17:16 -04:00
David Harris	07f2064c19	Touched up TLB D and A bit checks	2021-07-04 18:17:09 -04:00
bbracker	ceac0352f7	ICacheCntrl now reacts differently to InstrPageFaultF vs ITLBWriteF	2021-07-04 18:17:06 -04:00
Ross Thompson	b2c5c3f637	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-04 17:07:57 -05:00
David Harris	b0f199b574	Fixed TLB_ENTRIES merge conflict and handling of global PTEs	2021-07-04 18:05:22 -04:00
Ross Thompson	02721c29dc	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-04 16:54:31 -05:00
Ross Thompson	17f37f21ff	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-04 16:53:16 -05:00
David Harris	8b707f7703	Added ASID & Global PTE handling to TLB CAM	2021-07-04 17:53:08 -04:00
David Harris	80666f0a71	Added ASID & Global PTE handling to TLB CAM	2021-07-04 17:52:00 -04:00
Ross Thompson	a252416535	Removed the TranslationVAdrQ as it is not necessary.	2021-07-04 16:49:34 -05:00
bbracker	7191c03282	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-04 17:20:55 -04:00
bbracker	9c84ab436a	for GPIO give priority to clearing interrupts	2021-07-04 17:20:16 -04:00
Ross Thompson	7f62808544	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-04 16:19:39 -05:00
David Harris	07ef67e537	Restructured TLB Read as AND-OR operation with one-hot match/read line	2021-07-04 17:01:22 -04:00
David Harris	8337d6df68	Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders	2021-07-04 16:33:13 -04:00
David Harris	c281539f36	TLB cleanup	2021-07-04 14:59:04 -04:00
Ross Thompson	5b70eb86b0	relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic.	2021-07-04 13:49:38 -05:00
David Harris	81742ef9e2	TLB cleanup	2021-07-04 14:37:53 -04:00
David Harris	152923e552	TLB minor organization	2021-07-04 14:30:56 -04:00
David Harris	7e22ae973e	Fixed MPRV and MXR checks in TLB	2021-07-04 13:20:29 -04:00
David Harris	1b39481a16	TLB mux and swizzling cleanup	2021-07-04 12:53:52 -04:00
David Harris	735f3b4217	Replaced generates with arrays in TLB	2021-07-04 12:32:27 -04:00
David Harris	67e191c6f3	Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries	2021-07-04 11:39:59 -04:00
David Harris	ccd9c05303	Switched to array notation for pmpchecker	2021-07-04 10:51:56 -04:00
David Harris	accbebfa6f	Commented out some unused modules	2021-07-04 01:40:27 -04:00
David Harris	e90c532258	Merge conflict on linux-waves.do	2021-07-04 01:22:10 -04:00
David Harris	9645b023c9	Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.	2021-07-04 01:19:38 -04:00
bbracker	d68791a6d9	optionally output GDB-formatted instruction list to main buildroot folder	2021-07-03 17:25:19 -04:00
Ross Thompson	9f16d08d0d	removed mmustall and finished port annotations on ptw and lsuArb.	2021-07-03 16:06:09 -05:00
Ross Thompson	043f1e10c5	Added explicit names to lsu, lsuarb and pagetable walker to make the code refactoring process eaiser.	2021-07-03 15:51:25 -05:00
Ben Bracker	d8facacef6	src/cache/ICacheCntrl.sv	2021-07-03 11:24:41 -05:00
Ben Bracker	eff5a1b90f	fix ICache indenting	2021-07-03 11:11:07 -05:00
David Harris	1fa4abf7b6	Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker	2021-07-03 03:29:33 -04:00
David Harris	d44916dacf	Cleaned up PMA/PMP checker unused code	2021-07-03 02:25:31 -04:00
Ben Bracker	59b177beac	stop busybear from hanging	2021-07-02 17:22:09 -05:00
David Harris	0bd18ff662	Fixed PMPCFG read faults	2021-07-02 17:08:13 -04:00
Ross Thompson	cf688bd3f6	Fixed up the physical address generation for 64 bit page table walker.	2021-07-02 15:49:32 -05:00
Ross Thompson	8e3149517a	Fixed up the bit widths on the page table walker for rv32.	2021-07-02 15:45:05 -05:00
Ross Thompson	7b3716c281	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-02 13:56:49 -05:00
Katherine Parry	20d6e57aa5	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-02 12:56:53 -04:00
Katherine Parry	308c9ccaac	FPU update - missing files	2021-07-02 12:53:05 -04:00
Ross Thompson	dbd33465e1	Merge branch 'main' into bigbadbranch	2021-07-02 11:52:26 -05:00
David Harris	5b6ebd7935	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-02 12:52:20 -04:00
Katherine Parry	30ff212ca8	FPU update	2021-07-02 12:40:58 -04:00
David Harris	76a43eb468	Optimized PMP checker logic and added support for configurable number of PMP registers	2021-07-02 11:05:25 -04:00
David Harris	c85e0df1ff	Optimized PMP checker logic and added support for configurable number of PMP registers	2021-07-02 11:04:13 -04:00
Ross Thompson	d1a366472f	reverted change to the imperas tests order. Accidently commited change which placed the virtual memory tests first.	2021-07-01 18:04:43 -05:00
Ross Thompson	118dfa9cec	added page table walker fault exit for icache.	2021-07-01 17:59:55 -05:00
Ross Thompson	61027f650c	OMG. It's working!	2021-07-01 17:37:53 -05:00
Ross Thompson	6916784354	Fixed tab space issue.	2021-07-01 17:17:53 -05:00
Ross Thompson	2dc349ea6f	Fixed the wrong virtual address write into the dtlb.	2021-07-01 16:55:16 -05:00
Teo Ene	ec21126474	Flow updated for 90nm	2021-07-01 13:32:42 -05:00
Ross Thompson	88a18496cf	Got some stores working in virtual memory.	2021-07-01 12:49:09 -05:00
Ross Thompson	157b1b31bf	Icache ITLB interlock fix.	2021-06-30 19:24:59 -05:00
Ross Thompson	002c32d2ad	The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay.	2021-06-30 17:02:36 -05:00
Ross Thompson	9ec624702d	Major rewrite of ptw to remove combo loop.	2021-06-30 16:25:03 -05:00
Ross Thompson	b2d8ba6742	The icache now correctly interlocks with the PTW on TLB miss.	2021-06-30 11:24:26 -05:00
Ross Thompson	dd84f2958e	Page table walker now walks the table. ... Added interlock so the icache stalls. Page table walker not walking correctly, goes to fault state.	2021-06-29 22:33:57 -05:00
Katherine Parry	0c2b7a1132	FPU control signals changed and FMA works	2021-06-28 18:53:58 -04:00
Ross Thompson	bc9c944ba0	Don't use this branch walker still broken.	2021-06-28 17:26:11 -05:00
bbracker	751e606fb7	trying out Noah and Kaveh's proposed hack for which CSRs to update for QEMU MMU bug	2021-06-26 08:30:58 -04:00
bbracker	17afd9e5e8	temporarily disable PMP checking for EBU accesses.	2021-06-26 07:19:51 -04:00
bbracker	74833dc68c	split intermediate GDB output file into smaller files for better debug experience	2021-06-26 07:18:26 -04:00
Ross Thompson	d80ebab941	AMO and LR/SC instructions now working correctly. ... Page table walking is not working.	2021-06-25 15:42:07 -05:00
Ross Thompson	57a7074800	Some progress. Had to change how the page table walker got it's ready.	2021-06-25 15:07:41 -05:00
Ross Thompson	b4a788c341	Working through a combo loop.	2021-06-25 14:49:27 -05:00
Ross Thompson	d6c19e73f4	Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.	2021-06-25 11:05:17 -05:00
bbracker	13cf7c0934	linux testbench now ignores HWRITE glitches caused by flush glitches	2021-06-25 09:28:52 -04:00
bbracker	5b47da21ba	made testbench-linux's PCDwrong be FlushD	2021-06-25 08:15:19 -04:00
bbracker	34dbad967d	ah merge; I checked and this does pass all of regression except lints	2021-06-25 07:37:06 -04:00
bbracker	192171826b	changed SC M-to-E fowarding to W-to-E forwarding to improve critical path	2021-06-25 07:18:38 -04:00
Kip Macsai-Goren	d7e518991e	Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.	2021-06-24 20:01:11 -04:00
Kip Macsai-Goren	ac597d78c8	Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.	2021-06-24 19:59:29 -04:00
Katherine Parry	7e3483b283	FPU forwarding reworked pt.1	2021-06-24 18:39:18 -04:00
bbracker	2155a4e485	Revert "fixed forwarding" ... This reverts commit 86e369df52.	2021-06-24 17:39:37 -04:00
Ross Thompson	6bab454b17	Works until pma checker breaks the simulation by reading HADDR rather than data physical address.	2021-06-24 14:42:59 -05:00
Ross Thompson	c02141697d	Fixed combo loop in between the page table walker and i/dtlb.	2021-06-24 13:47:10 -05:00
Ross Thompson	aeeaf6d919	Progress.	2021-06-24 13:05:22 -05:00
bbracker	86e369df52	fixed forwarding	2021-06-24 11:20:21 -04:00
bbracker	2d9c91096b	make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses	2021-06-24 08:35:00 -04:00
bbracker	53d545cdfe	regression can overcome the fact that buildroots UART prints stuff	2021-06-24 02:00:01 -04:00
bbracker	cee468b21a	whoops meant to remove notifications from busybear, not buildroot	2021-06-24 01:54:46 -04:00
bbracker	13df69abdb	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-24 01:42:41 -04:00
bbracker	be962cb1ff	overhauled linux testbench and spoofed MTTIME interrupt	2021-06-24 01:42:35 -04:00
Kip Macsai-Goren	c8f80967a6	added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.	2021-06-23 19:59:06 -04:00
Ross Thompson	286b4b5b26	Partial addition of page table walker arbiter.	2021-06-23 17:03:54 -05:00
Ross Thompson	9b8bcb8e57	Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two. ... Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB. Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP. With Kip.	2021-06-23 16:43:22 -05:00
Katherine Parry	8eed89616c	fpu clean-up	2021-06-23 16:42:40 -04:00
Ross Thompson	f74ecbb81e	Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.	2021-06-23 15:13:56 -05:00
Ross Thompson	349f6a9471	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-06-23 09:34:42 -05:00
David Harris	a514554eeb	Reduced complexity of pmpadrdec	2021-06-23 03:03:52 -04:00
David Harris	2060a5c2f8	Reduced complexity of pmpadrdec	2021-06-23 02:31:50 -04:00
David Harris	fa51ab9f68	Refactored pmachecker to have adrdecs used in uncore	2021-06-23 01:41:00 -04:00
David Harris	6be0a3b8df	renamed dmem to lsu and removed adrdec module from pmpadrdec	2021-06-22 23:03:43 -04:00
bbracker	fc851ca795	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-22 18:28:30 -04:00
bbracker	303f8e2a7f	give EBU a dedicated PMA unit as just an address decoder	2021-06-22 18:28:08 -04:00
Ross Thompson	67cf2e1c90	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-06-22 15:47:16 -05:00
Katherine Parry	353a27f12f	rv64f FLW passes imperas tests	2021-06-22 16:36:16 -04:00
Kip Macsai-Goren	7e06a3c04d	Fixed mask assignment error, made usage, variables more clear	2021-06-22 13:31:06 -04:00
Kip Macsai-Goren	2c41da0275	Continued fixing fsm to work right with svmode	2021-06-22 13:29:49 -04:00
Kip Macsai-Goren	3e19eba20d	updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop	2021-06-22 11:21:11 -04:00
bbracker	9b27cd6fb7	added slack notifier for long sims	2021-06-22 08:31:41 -04:00
Ross Thompson	f79e5eaa47	Icache now uses physical lenght bits rather than XLEN.	2021-06-21 16:41:09 -05:00
Ross Thompson	3cbe4c9bc2	Improved some names in icache.	2021-06-21 16:40:37 -05:00
David Harris	7930c2ebb4	Commented out 100k tests to improve speed	2021-06-21 01:43:18 -04:00
David Harris	5d6dc82db2	Added Physical Address and Size to PMA Checker/MMU	2021-06-21 01:27:02 -04:00
David Harris	1ec90a5e1f	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
David Harris	d2ec04564b	Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals	2021-06-20 22:59:04 -04:00
bbracker	23f479d225	remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR	2021-06-20 22:38:25 -04:00
bbracker	bf3c2dc089	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-20 22:29:40 -04:00
bbracker	3000c27acd	linux actually uses FPU now!	2021-06-20 22:29:21 -04:00
Katherine Parry	2b67f25683	all rv64f instructions except convert, divide, square root, and FLD pass	2021-06-20 20:24:09 -04:00
bbracker	2643130c41	read from MSTATUS workaround because QEMU has incorrect MSTATUS	2021-06-20 10:11:39 -04:00
bbracker	14ae87ff0a	testbench update b/c QEMU extends 32b CSRs to 64b	2021-06-20 09:24:19 -04:00
bbracker	83a0a37f8e	make xCOUNTEREN what buildroot expects it to be	2021-06-20 09:22:31 -04:00
bbracker	dc26f2a6d0	whoops wavedo typo	2021-06-20 05:36:54 -04:00
bbracker	c77aabdc6f	make buildroot ignore SSTATUS because QEMU did not originally log it	2021-06-20 05:31:24 -04:00
bbracker	918ff5093a	MSTATUS workaround	2021-06-20 04:48:09 -04:00
bbracker	069a79fafd	workaround for ignoring MTIME	2021-06-20 02:26:39 -04:00
bbracker	086f031b84	remove lingering busybear stuff from buildroot do files	2021-06-20 00:50:53 -04:00
bbracker	8462f248aa	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-20 00:40:44 -04:00
bbracker	d62d9a7aac	make buildroot waves only turn on after a user-specified point	2021-06-20 00:39:30 -04:00
Ross Thompson	70c45a5349	Revert "Icache now uses physical lenght bits rather than XLEN." ... This reverts commit 16266d978a.	2021-06-19 08:58:34 -05:00
Ross Thompson	868ddce5f2	Revert "Improved some names in icache." ... This reverts commit a57c63aa7b.	2021-06-19 08:58:32 -05:00
bbracker	a3eafc6e5b	change buildroot config to use relative path for testvectors	2021-06-18 22:28:07 -04:00
bracker	26512348b0	gitignore merge	2021-06-18 21:12:05 -05:00
bracker	34f17b90ea	handle tera usernames more gracefully	2021-06-18 21:11:14 -05:00
bbracker	1781ae9c93	on-Tera solution for sym linking to linux testvectors	2021-06-18 22:01:18 -04:00
bracker	cd7d403f92	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-18 20:41:01 -05:00
bracker	0addf4a297	script support for copying large files from tera	2021-06-18 20:40:19 -05:00
bbracker	cb949851d9	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-18 17:37:49 -04:00
bbracker	8d242d73b5	fixed PCtext error by using blocking assignments	2021-06-18 17:37:40 -04:00
Ross Thompson	99e3a0db28	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-06-18 12:24:42 -05:00
Ross Thompson	a57c63aa7b	Improved some names in icache.	2021-06-18 12:22:41 -05:00
Ross Thompson	16266d978a	Icache now uses physical lenght bits rather than XLEN.	2021-06-18 12:02:59 -05:00
David Harris	33312caeb1	Restored wally-busybear testbench now that graphical sim is working	2021-06-18 12:36:25 -04:00
bbracker	03a45aeef1	restore graphical buildroot sim	2021-06-18 11:58:16 -04:00
Abe	a0a4b09c94	Updated directory coremark_bare's wally-config file to define PMP_ENTRIES	2021-06-18 11:46:25 -04:00
bbracker	5095c73dde	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-18 09:49:37 -04:00
bbracker	4f50dd575d	buildroot added to regression because it passes regression	2021-06-18 09:49:30 -04:00
David Harris	580ac1c4df	Made MemPAdrM and related signals PA_BITS wide	2021-06-18 09:36:22 -04:00
David Harris	de221ff2d0	Changed physical addresses to PA_BITS in size in MMU and TLB	2021-06-18 09:11:31 -04:00
bbracker	c25905ac70	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-18 08:15:40 -04:00
bbracker	faae30c31c	remove unused testbench-busybear.sv	2021-06-18 08:15:19 -04:00
David Harris	df7e373c69	Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX	2021-06-18 08:13:15 -04:00
David Harris	35c74348a4	allow all size memory access in CLINT; added underscore to peripheral address symbols	2021-06-18 08:05:50 -04:00
David Harris	336936cc39	Cleaned up name of MTIME register in CSRC	2021-06-18 07:53:49 -04:00
David Harris	de3a0c644b	Further cleaning of PMA checker	2021-06-17 22:27:39 -04:00
David Harris	679e507cc6	Added SUPPORTED to each peripheral in each config file	2021-06-17 21:36:32 -04:00
David Harris	54b6a2dcad	added inputs to pmaadrdec	2021-06-17 18:54:39 -04:00
David Harris	da8eb7749f	Started simplifying PMA checker	2021-06-17 16:28:06 -04:00
bbracker	2bee4eabab	added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version	2021-06-17 12:09:10 -04:00
bbracker	b65adbea63	enable TIME CSR for 32 bit mode as well	2021-06-17 11:34:16 -04:00
bbracker	5a661a7392	provide time and timeh CSRs based on CLINT's counter	2021-06-17 08:38:30 -04:00
bbracker	5b96f7fbd7	making linux waveforms more useful	2021-06-17 08:37:37 -04:00
bbracker	9bc5ddf5f2	PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable	2021-06-17 05:19:36 -04:00
bbracker	b459d0cc80	changed parsedCSRs2] to parsedCSRs	2021-06-17 05:18:14 -04:00
bbracker	c4983f4388	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-17 00:50:14 -04:00
bbracker	6625f74a85	still not sure if QEMU workaround is correct, but here is all linux progress so far	2021-06-17 00:50:02 -04:00
bbracker	7b98e7aa2f	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
bbracker	3b9ecc8275	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-16 16:17:53 -04:00
bracker	f99c91553f	chmod +x'd privileged testgen scripts	2021-06-16 10:28:57 -05:00
bbracker	9c883054c7	fixed incorrect expectation fof CLINT spec	2021-06-15 19:24:24 -04:00
bbracker	cd00e04943	Merge remote-tracking branch 'origin/fixPrivTests' into main	2021-06-15 09:57:46 -04:00
Katherine Parry	4177f4f148	Updated FMA	2021-06-14 13:42:53 -04:00
David Harris	c6ff11c22e	disabled Verilator WIDTH warnings in ICCacheCntrl	2021-06-12 19:50:06 -04:00
Ross Thompson	294f01cbd8	fixed the mtime register.	2021-06-11 13:50:13 -05:00
James E. Stine	11c88c15d5	Put repository of fpdivsqrt with RTL-based adder instead of structural implementation	2021-06-11 14:35:22 -04:00
bracker	8794bf1afa	attempt no 1: just change out x28s for x31s	2021-06-11 12:39:28 -05:00
David Harris	49b5fa3994	Reverted MIDELEG and MEDELEG to XLEN so busybear passes	2021-06-10 23:47:32 -04:00
David Harris	e41a87be23	Restored counter events	2021-06-10 11:18:58 -04:00
David Harris	d386929c0e	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-10 10:47:55 -04:00
David Harris	802238643a	Removed two cycles of latency from the DTIM	2021-06-10 10:30:24 -04:00
bbracker	f272cd46d8	peripheral lint fixes	2021-06-10 10:19:10 -04:00
bbracker	d4aeb1c387	merge	2021-06-10 10:03:01 -04:00
bbracker	0321d74562	attempt to fix regression by adding PMP_ENTRIES to configs	2021-06-10 09:59:26 -04:00
bbracker	d9022551c2	buildroot progress -- able to mimic GDB output	2021-06-10 09:58:20 -04:00
bbracker	79e798a641	UART improved and added more reg read side effects	2021-06-10 09:53:48 -04:00
David Harris	3e8026dc21	Configurable number of performance counters	2021-06-10 09:41:26 -04:00
David Harris	75870a16d7	Restored PCCorrectE declaration in IFU	2021-06-09 21:09:16 -04:00
David Harris	0ffbd03139	More verilator fixes, but bpred is broken	2021-06-09 21:03:03 -04:00
David Harris	c7e57aeb1a	removed verilator lint_off WIDTH	2021-06-09 21:01:44 -04:00
David Harris	01d6ca1e2a	Fixed lint WIDTH errors	2021-06-09 20:58:20 -04:00
David Harris	2952550db7	More PMP entries	2021-06-08 15:33:06 -04:00
David Harris	90e5781471	Start to parameterize number of PMP Entries	2021-06-08 15:29:22 -04:00
Kip Macsai-Goren	a95a7a7b82	working version with new mmu comments, old boottim values	2021-06-08 15:20:25 -04:00
Kip Macsai-Goren	2155cb2e91	merge of reverted main into up to date main	2021-06-08 14:57:43 -04:00
Kip Macsai-Goren	361c71c5e9	reverted to working version with new mmu comments	2021-06-08 14:56:00 -04:00
David Harris	b613f46c2d	Resized BOOT TIM to 1 KB	2021-06-08 14:04:32 -04:00
Kip Macsai-Goren	aab7bd94f7	Merge small mmu changes into main	2021-06-08 14:00:26 -04:00
Kip Macsai-Goren	d6f47d5917	making mmu branch line up with main	2021-06-08 13:59:03 -04:00
Kip Macsai-Goren	e209dbcf50	some cleanup of signals, not done yet	2021-06-08 13:39:32 -04:00
bbracker	cc91c774a6	Ah big ole merge! Passes sim-wally-batch and linting, so should be fine	2021-06-08 12:41:25 -04:00
bbracker	e7e4105931	* GPIO comprehensive testing ... * MEPC more aware if M stage has actually committed * UART interrupt testing progress * UART added read IIR side effect of lowering THRE intr	2021-06-08 12:32:46 -04:00
Kip Macsai-Goren	49515245d9	remove redundant decodes, fixed mmu logic ins/outs	2021-06-07 19:23:30 -04:00
Kip Macsai-Goren	1e174a8244	got rid of some underscores in filenames, modules	2021-06-07 18:54:05 -04:00
Kip Macsai-Goren	c96695b1b6	implemented simpler page mixers, cleaned up a bit	2021-06-07 18:32:34 -04:00
Kip Macsai-Goren	b27abc53e8	began updating cam line to reduce muxes, confusion	2021-06-07 17:03:31 -04:00
Kip Macsai-Goren	6a63ad04d2	regression working partially done page mask	2021-06-07 17:02:31 -04:00
David Harris	9efbffdee5	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-07 16:14:13 -04:00
David Harris	43a690dc42	Simplified superpage matching	2021-06-07 16:11:28 -04:00
Katherine Parry	0acf665a8b	lint is clean	2021-06-07 14:22:54 -04:00
bbracker	28c6d60150	temporarily removing buildroot from regression until it is regenerated	2021-06-07 13:20:50 -04:00
David Harris	2ae5ca19b5	Continued merge	2021-06-07 12:49:47 -04:00
David Harris	ff62000e2c	Second attept to commit refactoring config files	2021-06-07 12:37:46 -04:00
David Harris	dc0b19dfaa	Merge difficulties	2021-06-07 09:50:23 -04:00
David Harris	d5ec797ba4	Refactored configuration files and renamed testbench-busybear to testbench-linux	2021-06-07 09:46:52 -04:00
Katherine Parry	75a6097467	fixed lint warnings for fpu and lzd	2021-06-05 12:06:33 -04:00
Kip Macsai-Goren	49200bd922	Cleaned up some unused signals	2021-06-04 21:04:19 -04:00
Kip Macsai-Goren	22e8e06ac7	moved privilege dfinitions into wally-constants, upgraded relevant includes	2021-06-04 17:55:07 -04:00
Kip Macsai-Goren	037aa6fa89	Merge branch 'mmu' into main ... new mmu unit and moving pmp/pma now passes regression except for lint and buildroot	2021-06-04 17:07:56 -04:00
Kip Macsai-Goren	3493027bf5	added shared constants file list of includes	2021-06-04 17:05:47 -04:00
Kip Macsai-Goren	1ae529c450	restructured so that pma/pmp are a part of mmu	2021-06-04 17:05:07 -04:00
Ross Thompson	41a1e6112a	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-06-04 15:16:39 -05:00
Ross Thompson	7406e33b61	Continued I-Cache cleanup. ... Removed strange mux on InstrRawD along with the select logic.	2021-06-04 15:14:05 -05:00
Ross Thompson	191f7e61fd	Moved I-Cache offset selection mux to icache.sv (top level). ... When we switch to set associative this is will be more efficient.	2021-06-04 13:49:33 -05:00
Ross Thompson	e0d0fdd708	Cleaned up the I-Cache memory.	2021-06-04 13:36:06 -05:00
Katherine Parry	fc65aedbd6	Double-precision FMA instructions	2021-06-04 14:00:11 -04:00
Ross Thompson	fdef8df76b	Reorganized the icache names.	2021-06-04 12:53:42 -05:00
Ross Thompson	7c44f19925	Relocated the icache to the cache directoy.	2021-06-04 12:23:46 -05:00
David Harris	a26bf37be8	Started MMU	2021-06-04 11:59:14 -04:00
David Harris	4f71964529	Fixed RV32 MMU constants	2021-06-04 09:15:42 -04:00
David Harris	0674f5506e	moved shared constants to a shared directory	2021-06-03 22:41:30 -04:00
Kip Macsai-Goren	8fb2ee6e86	added support for sv48 and some docs on how to use these files	2021-06-03 14:32:12 -04:00
Kip Macsai-Goren	1ea9b94cf1	added tests for SV48 and translation off with vmem	2021-06-03 14:28:52 -04:00
bbracker	ad3b103a86	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-03 10:03:26 -04:00
bbracker	4e765ee1c5	expanded GPIO testing and caught small GPIO bug	2021-06-03 10:03:09 -04:00
Ross Thompson	e50a1ef5e4	Fixed a few lint errors, ... clock gater was wrong, missing signal definitions in branch predictor.	2021-06-02 09:33:24 -05:00
bbracker	a683dd7fde	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-02 10:03:23 -04:00
bbracker	2c77a13c08	fixed InstrValid signals and implemented less costly MEPC loading	2021-06-02 10:03:19 -04:00
Kip Macsai-Goren	5187574e8a	implemented Sv48.	2021-06-01 17:50:37 -04:00
Kip Macsai-Goren	40cfa86935	Edited and added constants to support SV48	2021-06-01 17:49:45 -04:00
James E. Stine	eba7ce64f5	delete div.bak	2021-06-01 17:39:54 -04:00
Ross Thompson	babcea195a	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-06-01 15:20:37 -05:00
Ross Thompson	0670c57fd2	The clock gater was not implemented correctly. Now it is level sensitive to a low clock.	2021-06-01 15:05:22 -05:00
James E. Stine	564d7c4adb	Minor cosmetic update to fpu.sv	2021-06-01 15:45:32 -04:00
James E. Stine	2eeb12c674	Updates to muldiv.sv for 32-bit div/rem	2021-06-01 15:31:07 -04:00
Ross Thompson	fe22fd2db8	added clock gater to floating point divider to speed up simulation time.	2021-06-01 13:46:21 -05:00
Ross Thompson	7f1653f073	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-06-01 12:42:21 -05:00
Ross Thompson	997c13a521	Forgot to include the new gshare predictor file.	2021-06-01 12:42:03 -05:00
Kip Macsai-Goren	fac2431add	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-01 13:20:39 -04:00
Ross Thompson	ab509614bb	Changed to bp config to use gshare.	2021-06-01 12:14:58 -05:00
Ross Thompson	89ad4477e4	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-06-01 11:33:12 -05:00
Ross Thompson	857f59ab5c	Now have global history working correctly.	2021-06-01 10:57:43 -05:00
James E. Stine	ddbdd0d5a2	Modify muldiv.sv to handle W instructions for 64-bits	2021-05-31 23:27:42 -04:00
Ross Thompson	f6c88666cf	may have fixed the global branch history predictor. ... The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired.	2021-05-31 16:11:12 -05:00
Kip Macsai-Goren	0fe63282f8	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-31 11:01:15 -04:00
James E. Stine	46a232b862	Cosmetic changes on integer divider	2021-05-31 09:16:30 -04:00
James E. Stine	9954d16fc9	Add enhancements to integer divider including: ... - better comments - optimize FSM to end earlier - passes for 32-bit or 64-bit depending on parameter to intdiv Left div.bak in just in case have to revert back to original for now.	2021-05-31 09:12:21 -04:00
James E. Stine	12c34c25f3	Modify elements of generics for LZD and shifter wrote for integer ... divider.	2021-05-31 08:36:19 -04:00
bbracker	39ae743543	turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)	2021-05-28 23:11:37 -04:00
Kip Macsai-Goren	690815ca51	made priority encoder parameterizable	2021-05-28 18:09:28 -04:00
Ross Thompson	8a035104ac	It's a bit sloppy, but the global history predictor is working correctly now. ... There were two major bugs with the predictor. First the update mechanism was completely wrong. The PHT is updated with the GHR that was used to lookup the prediction. PHT[GHR] = Sat2(PHT[GHR], branch outcome). Second the GHR needs to be updated speculatively as the branch is predicted. This is important so that back to back branches' GHRs are not the same. The must be different to avoid aliasing. Speculation of the GHR update allows them to be different. On mis prediction the GHR must be reverted. This implementation is a bit sloppy with names and now the GHR recovery is performed. Updates to follow.	2021-05-27 23:06:28 -05:00
Katherine Parry	778ba6bbf5	classify unit created and passes imperas tests	2021-05-27 18:53:55 -04:00
Katherine Parry	1459d840ed	All compare instructions pass imperas tests	2021-05-27 15:23:28 -04:00
Katherine Parry	309e6c3dc1	FADD and FSUB imperas tests pass	2021-05-26 12:33:33 -04:00
James E. Stine	bb99480fca	delete old file for FPregfile	2021-05-26 09:13:09 -05:00
James E. Stine	77260643eb	Add regression test for fpadd	2021-05-26 09:12:37 -05:00
Katherine Parry	e7190b0690	renamed top level FPU wires	2021-05-25 20:04:34 -04:00
Kip Macsai-Goren	45e7628e90	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-25 15:28:19 -04:00
Ross Thompson	fec40a1b75	fixed bug with icache miss spill fsm branch.	2021-05-25 14:26:22 -05:00
James E. Stine	bb5404e14a	Update FPregfile to use more compact code and better structure for ease in reading	2021-05-25 13:21:59 -05:00
Ross Thompson	063e458ff0	Merge remote-tracking branch 'refs/remotes/origin/main' into main	2021-05-24 23:25:36 -05:00
Ross Thompson	16e037b8e9	Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF.	2021-05-24 23:24:54 -05:00
Kip Macsai-Goren	8ae43a15d4	partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields	2021-05-24 20:59:26 -04:00
James E. Stine	c4f3f2f783	Minor cosmetic elements on div.sv	2021-05-24 19:30:28 -05:00
James E. Stine	295263e122	Mod for DIV/REM instruction and update to div.sv unit	2021-05-24 19:29:13 -05:00
bbracker	f755827c90	slightly more path independence for using verilator	2021-05-24 18:11:56 -04:00
Ross Thompson	c5310e85c1	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-05-24 14:28:41 -05:00
Katherine Parry	90d5fdba04	FMV.X.D imperas test passes	2021-05-24 14:44:30 -04:00
Ross Thompson	65632cb7c9	Fixed minor bug in instruction class decoding.	2021-05-24 13:41:14 -05:00
Ross Thompson	72f77656a3	Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link).	2021-05-24 12:37:16 -05:00
Ross Thompson	8bf411c640	Updated branch predictor tests/benchmarks.	2021-05-24 11:13:33 -05:00
James E. Stine	6f38b7633c	Update header for FPadd	2021-05-24 08:28:16 -05:00
Katherine Parry	70968a4ec3	FSD and FLD imperas tests pass	2021-05-23 18:33:14 -04:00
bbracker	846553ac7d	improved PLIC test organization	2021-05-21 15:13:02 -04:00
James E. Stine	e70136ec78	Minor testbench updates to rv64icfd	2021-05-21 09:41:21 -05:00
James E. Stine	23769e36a5	Update to testbench-imperase for rv64icfd	2021-05-21 09:28:44 -05:00
James E. Stine	fed3b30557	Update to FLD/FSD testbench	2021-05-21 09:26:55 -05:00
James E. Stine	c89d3e01bb	Update to rv64icfd wally-config to run through FP tests	2021-05-21 09:22:17 -05:00
Katherine Parry	4db7f3065c	FMV.D.X imperas test passes	2021-05-20 22:18:33 -04:00
Katherine Parry	06af239e6c	FMV.D.X imperas test passes	2021-05-20 22:17:59 -04:00
bbracker	1d3db5ead5	small bit of busybear debug progress	2021-05-19 20:18:00 -04:00
bbracker	bf6337f2f7	plic implementation optimizations	2021-05-19 18:10:48 +00:00
bbracker	979a9bf037	commented out MSTATUS test	2021-05-19 12:38:01 -04:00
James E. Stine	304e70d3ae	Update rv64icfd batch script	2021-05-18 16:01:53 -05:00
James E. Stine	44dc665fc5	Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)	2021-05-18 13:48:44 -05:00
bbracker	e4d51ebef5	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-18 14:33:40 -04:00
bbracker	c495fc71f1	changed lint script to use absolute path for verilator because cron jobs stink at using paths	2021-05-18 14:33:22 -04:00
David Harris	26531f2634	fixed rv64mmu makefile	2021-05-18 14:25:55 -04:00
David Harris	5da159d17e	Removed rv64wally	2021-05-18 14:08:46 -04:00
David Harris	4d264c6f61	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/regression/vish_stacktrace.vstf	2021-05-18 14:01:19 -04:00
Katherine Parry	9464c9022d	floating point infinite loop removed from imperas tests	2021-05-18 10:42:51 -04:00
bbracker	f00eb22700	fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions	2021-05-17 19:25:54 -04:00
bbracker	e4c90f503a	regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench	2021-05-17 18:44:47 -04:00
David Harris	9901f54b15	Deleted vish_stacktrace	2021-05-17 18:39:01 -04:00
James E. Stine	e808b06b82	Forgot initialization config for div - apologies	2021-05-17 17:12:27 -05:00
Elizabeth Hedenberg	b818ce608a	commit ehedenberg coremark	2021-05-17 18:02:35 -04:00
James E. Stine	5506efc115	Add 32/64-bit shifter for update to shifter block	2021-05-17 17:02:13 -05:00
James E. Stine	3d3e3434f6	Cleanup of regression	2021-05-17 16:58:15 -05:00
James E. Stine	daf780b9c2	Mod Imperas Testbench for updated Div/Rem	2021-05-17 16:56:30 -05:00
James E. Stine	865b3ee219	Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version	2021-05-17 16:48:51 -05:00
Thomas Fleming	b9e099d53c	Fix comment	2021-05-14 08:06:07 -04:00
Thomas Fleming	6aa04af38d	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-05-14 07:40:08 -04:00
Thomas Fleming	ea4e76938e	Remove busy-mmu and fix missing signal	2021-05-14 07:14:20 -04:00
Thomas Fleming	e27bc1cbf7	Clean up MMU code	2021-05-14 07:12:32 -04:00
Elizabeth Hedenberg	170f072b52	pushing coremark to main branch	2021-05-11 21:33:39 -04:00
Jarred Allen	041149eaf7	Minor fixes in regression	2021-05-09 13:57:09 -04:00
Jarred Allen	c7f400262c	Fix bug in regression script	2021-05-06 12:56:57 -04:00
Domenico Ottolia	e3624ab2e6	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-05-04 20:22:31 -04:00
Domenico Ottolia	88ab07d456	Forgot to add csr permission tests to testbench	2021-05-04 20:20:22 -04:00
Jarred Allen	be029ba02c	Clean up regression script and document it	2021-05-04 18:58:59 -04:00
ushakya22	682bc7b58e	Added mip tests to testbench	2021-05-04 15:36:06 -04:00
Thomas Fleming	1ec6ad14f6	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-05-04 15:22:21 -04:00
bbracker	8a7fc959eb	small synthesis fixes	2021-05-04 15:21:01 -04:00
Thomas Fleming	19ac77d3fa	Fix compiler warning in PMP checker	2021-05-04 15:18:08 -04:00
Domenico Ottolia	8398e653dd	Re-add medeleg tests to testbench	2021-05-04 14:42:20 -04:00
Ross Thompson	a03a63a5c7	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-04 13:04:20 -05:00
Ross Thompson	21acc45121	Fixed synthesis bug with icache valid bit.	2021-05-04 13:03:08 -05:00
ushakya22	2e225bd756	Updated CSR tests	2021-05-04 13:48:47 -04:00
Ross Thompson	52e4c49bbb	Fixed icache pcmux control for handling miss spill miss.	2021-05-04 11:05:01 -05:00
Thomas Fleming	44ea58b771	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-05-04 03:14:38 -04:00
Thomas Fleming	3a3c88f5b1	Fix bug in PMP checker ... Now we only enforce PMP regions if at least one is non-null	2021-05-04 03:14:07 -04:00
ushakya22	46f20745d7	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-04 02:22:17 -04:00
ushakya22	b805b98a8c	Added MIE tests to testbench	2021-05-04 02:22:01 -04:00
Thomas Fleming	c9e5af30fa	Disable PMP checker to fix test loops ... There is a bug in the PMP checker where S or U mode attempts to make a memory access while no PMP registers are set. We currently treat this as a failure, when this should instead be allowed.	2021-05-04 01:56:05 -04:00
Domenico Ottolia	1673ad6e27	Minor tweaks to mcause & scause tests	2021-05-04 01:33:49 -04:00
David Harris	45b0af497c	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-04 01:19:57 -04:00
David Harris	d68fe44446	Fixed testbench to produce error when signature.output doesn't exist	2021-05-04 01:19:44 -04:00
Thomas Fleming	41a19153cc	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-05-04 01:14:13 -04:00
Domenico Ottolia	67c7bfe34d	Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE	2021-05-04 01:04:12 -04:00
Domenico Ottolia	973f32da47	Fix 32 bit privileged tests!!!	2021-05-04 00:16:19 -04:00
Thomas Fleming	a3b5ae9742	Restore original order of tests	2021-05-03 23:50:21 -04:00
Thomas Fleming	ad40464557	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-05-03 23:15:39 -04:00
Thomas Fleming	803a69efe6	Enable mmu tests in testbench	2021-05-03 23:15:23 -04:00
Domenico Ottolia	c0f054556c	Fix bug with IllegalInstrFaultM not getting correct value	2021-05-03 22:48:03 -04:00
Domenico Ottolia	2669a6a0db	Run all tests	2021-05-03 22:38:59 -04:00
Domenico Ottolia	4d70e22a6a	Update cause tests to be longer	2021-05-03 22:38:26 -04:00
Domenico Ottolia	997c9ad5c0	Add mtvec and stvec tests to testbench	2021-05-03 22:19:50 -04:00
Shriya Nadgauda	780ad3eaf4	working testbench-imperas	2021-05-03 22:16:58 -04:00
Shriya Nadgauda	c5a306426a	finishing merge conflict changes	2021-05-03 22:15:05 -04:00
Shriya Nadgauda	b7159652f6	merge conflict fixes	2021-05-03 22:12:30 -04:00
Shriya Nadgauda	968994c04a	updated pipeline tests	2021-05-03 22:07:36 -04:00
Thomas Fleming	0254ca7bf6	Adjust attributes in PMA checker	2021-05-03 21:58:32 -04:00
David Harris	afd6153044	Rolled back fflush on uart. Use -syncio in Modelsim command line instead.	2021-05-03 20:04:44 -04:00
David Harris	d07a7fd0f8	Flush uart print statements on \n	2021-05-03 19:51:51 -04:00
David Harris	93466a0b2a	Flush uart print statements on \n	2021-05-03 19:41:37 -04:00
David Harris	e265aa4d41	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-03 19:37:56 -04:00
David Harris	58ce0fbbcc	Flush uart print statements on \n	2021-05-03 19:37:45 -04:00
Elizabeth Hedenberg	2d1d929485	coremark print statment	2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg	2a33673e3c	coremark updates	2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg	463ba1a2be	coremark directory changes	2021-05-03 19:35:06 -04:00
David Harris	b66c7b81de	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-03 19:29:01 -04:00
David Harris	233726e8d8	Flush uart print statements on \n	2021-05-03 19:25:28 -04:00
Ross Thompson	baf29454f1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-03 16:57:36 -05:00
Domenico Ottolia	0f10d577d2	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-05-03 17:56:05 -04:00
Ross Thompson	82b4d42f32	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-03 16:56:00 -05:00
Ross Thompson	7f38056879	fixed subtle typo in icache fsm. Was messing up hit spill hit. ... I believe the mibench qsort benchmark runs after this icache fix.	2021-05-03 16:55:36 -05:00
Domenico Ottolia	5ab86a690b	Fix bug that caused stvec to get the wrong value	2021-05-03 17:54:57 -04:00
Thomas Fleming	ba1afec621	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-05-03 17:38:13 -04:00
Thomas Fleming	eda5a267ee	Implement PMP checker and revise PMA checker	2021-05-03 17:37:42 -04:00
Thomas Fleming	8dce32fd22	Remove remnants of InstrReadC	2021-05-03 17:36:25 -04:00
Jarred Allen	7d509252a7	Add lint to regression	2021-05-03 17:32:05 -04:00
Ross Thompson	e145670b15	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-03 14:53:54 -05:00
Ross Thompson	cdb602c9ce	Removed combinational loops between icache and PMA checker.	2021-05-03 14:51:25 -05:00
Ross Thompson	19a93345b5	Reduced icache to 1 port memory.	2021-05-03 14:47:49 -05:00
David Harris	d7438929d4	Extended maximum signature length to 1M	2021-05-03 15:29:20 -04:00
Katherine Parry	ff5a809c26	fpu warnings fixed/commented	2021-05-03 19:17:09 +00:00
Thomas Fleming	cfe64e7c24	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/ebu/ahblite.sv	2021-05-03 14:02:19 -04:00
Ross Thompson	a54c231489	Eliminated extra register and fixed ports to icache. ... Still need to support physical tag check and write in icache memory. Still need to reduce to 1 port SRAM in icache. I would like to refactor the icache code.	2021-05-03 12:04:54 -05:00
bbracker	c643372e1d	merge conflict resolved -- Ross and I made the same fix	2021-05-03 10:10:42 -04:00
bbracker	9ab714e636	small rv64 plic test bugfix	2021-05-03 10:06:44 -04:00
Ross Thompson	c7b97d0339	Added back in function name to wave.do	2021-05-03 09:04:48 -05:00
Ross Thompson	c0a4b7cb17	Fixed typo in ifu for bypassing branch predictor. ... Fixed missing signal name in local history predictor.	2021-05-03 08:56:45 -05:00
David Harris	a37d9b5e8e	Fixed lint error in div	2021-05-03 09:26:12 -04:00
bbracker	9bde239143	ifu lint fixes	2021-05-03 09:25:22 -04:00
bbracker	2368b58cc9	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-03 09:23:52 -04:00
Noah Boorstin	b32128465c	busybear: remove now unneeded hack for fixed CSR issue	2021-05-01 15:17:04 -04:00
Katherine Parry	db95151d8d	fpu imperas tests run	2021-05-01 02:18:01 +00:00
bbracker	1fcd43e844	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-04-30 06:26:35 -04:00
bbracker	182bfdbb0e	rv32 plic test and lint fixes	2021-04-30 06:26:31 -04:00
Noah Boorstin	48d32c1daf	rollback regression to 400k instrs for busybear	2021-04-29 20:59:30 -04:00
Domenico Ottolia	d03ca20dc9	Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts	2021-04-29 20:42:14 -04:00
Ross Thompson	818c0abc89	Fixed memory size in configs for rv32ic and rv64ic. ... Removed warning on call to $fscanf.	2021-04-29 17:36:46 -05:00
Domenico Ottolia	c60c4f4adc	Minor improvements to scause test	2021-04-29 16:48:07 -04:00
Domenico Ottolia	c8a81779ca	Add machine-mode timer interrupts to mcause tests	2021-04-29 16:39:18 -04:00
Thomas Fleming	6e5fc107d9	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-04-29 16:30:00 -04:00
Domenico Ottolia	6fc04768f5	Same but don't break sim-wally this time	2021-04-29 15:33:27 -04:00
Domenico Ottolia	7ae5d4d11e	Add more exceptions to medeleg tests	2021-04-29 15:32:13 -04:00
ushakya22	9dfbfd5772	fix to pcm bug	2021-04-29 15:21:08 -04:00
ushakya22	77210527c1	Working MIE timer tests	2021-04-29 15:19:43 -04:00
Domenico Ottolia	4fae8088e3	Add medeleg tests	2021-04-29 15:02:36 -04:00
Jarred Allen	bf54c9b0b2	Enhance lint-wally functionality	2021-04-29 14:48:41 -04:00
Jarred Allen	ebd9c0ee29	Remove signal which no longer exists from default waves, so sim-wally works	2021-04-29 14:41:10 -04:00
Jarred Allen	8fd9cc679b	Fix compile error in branch predictor	2021-04-29 14:36:56 -04:00
Shreya Sanghai	1e57c6bb92	fixed bug in gshare, global and local history BP	2021-04-29 06:14:32 -04:00
Thomas Fleming	5f2bccd88f	Clean up PMA checker and begin PMP checker	2021-04-29 02:20:39 -04:00
Thomas Fleming	c62fdfb7b3	Remove unused waves from .do files	2021-04-29 02:19:46 -04:00
Thomas Fleming	18e0b353a9	Add mmu waves (commented) to busybear	2021-04-28 20:01:05 -04:00
Noah Boorstin	a4dad3403e	same but do that right this time	2021-04-28 14:27:28 -04:00
Domenico Ottolia	60dc6aaf48	Modify make file to make privileged tests always pass Imperas (for testing interrupts) & Add mtvec/stvec tests	2021-04-27 21:47:38 -04:00
Noah Boorstin	44606b6c19	busybear: respect branch predictor disable config	2021-04-27 15:52:18 -04:00
Ross Thompson	8ae28e7887	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-04-26 14:28:09 -05:00
Ross Thompson	72363f5c66	Added the ability to exclude branch predictor.	2021-04-26 14:27:42 -05:00
Noah Boorstin	ff1a6b63ed	ok but do that better	2021-04-26 14:38:05 -04:00
Noah Boorstin	0324329ed9	linux: start using internal branch predictor signal	2021-04-26 14:34:38 -04:00
Ross Thompson	afbb100860	Fixed issue with not saving the first cache block read on a miss spill.	2021-04-26 12:57:34 -05:00
Noah Boorstin	ee628e388a	minor busybear fixes	2021-04-26 13:24:39 -04:00
Ross Thompson	8e5409af66	Icache integrated! ... Merge branch 'icache-almost-working' into main	2021-04-26 11:48:58 -05:00
Ross Thompson	467a463c13	Reverted back the exe2memfile.pl script changes. Something I changed broke the load tests.	2021-04-26 10:44:27 -05:00
bbracker	31a0387136	merge cleanup; mem init is broken	2021-04-26 08:00:17 -04:00
bbracker	ba94fa3436	it says I need to merge in order to pull	2021-04-26 07:46:24 -04:00
bbracker	1cc0dcc83f	progress on bus and lrsc	2021-04-26 07:43:16 -04:00
Ross Thompson	6e803b724e	Merge branch 'tests' into icache-almost-working	2021-04-25 21:25:36 -05:00
bbracker	86946266cf	thomas fixed it before I did	2021-04-24 09:38:52 -04:00
bbracker	a3487a9e47	do script refactor	2021-04-24 09:32:09 -04:00
Thomas Fleming	c21bd8a463	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-04-23 20:12:27 -04:00
Thomas Fleming	e3672ca23f	Add address translation to busybear testbench	2021-04-23 20:12:20 -04:00
Thomas Fleming	288a6d82ce	Fix HSIZE and HBURST signal widths in PMA checker	2021-04-23 20:11:43 -04:00
David Harris	85eb6bcf1a	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-04-23 19:04:29 -04:00
David Harris	9415e00bfa	Fixed exe2memfile.pl to handle large files	2021-04-23 19:04:16 -04:00
Ross Thompson	27ef10df07	almost working icache.	2021-04-23 16:47:23 -05:00
Noah Boorstin	09755251bc	busybear	2021-04-23 17:32:37 -04:00
Shriya Nadgauda	c66e63ff70	adding pipeline testing	2021-04-23 14:19:17 -04:00
Jarred Allen	c91f1e197b	Remind people to run make allclean when a regression fails	2021-04-22 19:21:00 -04:00
Ross Thompson	020fb65adf	Fixed icache for 32 bit. ... Merge branch 'cache' into main	2021-04-22 16:45:29 -05:00
Ross Thompson	c42399bdb5	Yes. The hack to not repeat the d memory operation fixed this issue.	2021-04-22 15:22:56 -05:00
Thomas Fleming	da76b80991	Write PCM to TVAL registers	2021-04-22 16:17:57 -04:00
Thomas Fleming	8fee3b3872	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-04-22 15:37:19 -04:00
Thomas Fleming	00ce24e67c	Prepare to squash bad ahb accesses	2021-04-22 15:36:45 -04:00
Thomas Fleming	53c05d6a73	Clean up lint errors in fpu and muldiv ... booth.sv had an actual error where a signal was being assigned to too many bits. muldiv has a lot of non blocking assignments, so I suppressed those warnings so the linter output was readable.	2021-04-22 15:36:03 -04:00
Domenico Ottolia	6b4d2e9634	Fix misa synthesis bug (for real now)	2021-04-22 15:35:20 -04:00
Thomas Fleming	38236e9172	Implement first pass at the PMA checker	2021-04-22 15:34:02 -04:00
Thomas Fleming	73d9e7775c	Pass lint-wally arguments to verilator	2021-04-22 13:39:20 -04:00
Jarred Allen	5df6be3ad5	Add buildroot to regression test	2021-04-22 13:34:56 -04:00
Thomas Fleming	6d1a6694a8	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-04-22 13:20:12 -04:00
Thomas Fleming	6acaa313b5	Temporarily disable rv64 mmu test ... Will restore once cache revamp is pushed	2021-04-22 13:19:18 -04:00
bbracker	74b35ac57a	greatly improved PLIC register interface	2021-04-22 11:22:01 -04:00
Ross Thompson	d8ab7a5de2	Partially working icache. ... The current issue is a StallF is required to halt the icache from getting an updated PCF. However if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory. This keeps StallF high and the icache FSM is never allowed to complete.	2021-04-22 10:20:36 -05:00
Thomas Fleming	00b3e36b30	Refactor tlb_ram to use flop primitives	2021-04-22 01:52:43 -04:00
Thomas Fleming	ef80176e2c	Extend stall on leaf page lookups	2021-04-22 01:51:38 -04:00
Domenico Ottolia	fb8f244dab	Fix misa bug	2021-04-22 00:59:07 -04:00
Thomas Fleming	e336fbd108	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/ifu/ifu.sv	2021-04-21 20:01:08 -04:00
Thomas Fleming	4bae666fa1	Implement virtual memory protection	2021-04-21 19:58:36 -04:00
Ross Thompson	7b3735fc25	Fixed for the instruction spills.	2021-04-21 16:47:05 -05:00
Teo Ene	c7a21b05f7	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-04-21 16:06:33 -05:00
Teo Ene	ddc98e7d08	Fixed most relevant remaining synthesis compilation warnings with Ben	2021-04-21 16:06:27 -05:00
Noah Boorstin	cd7ea29ce6	buildroot: add workaround for weird initial MSTATUS state	2021-04-21 16:03:42 -04:00
Ross Thompson	532c8771ba	major progress. ... It's running the icache is imperas tests now. Compressed does not work yet.	2021-04-21 08:39:54 -05:00
Domenico Ottolia	44da1488ff	Add tests for stval and mtval	2021-04-21 02:31:32 -04:00
Domenico Ottolia	f63f16f486	Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file	2021-04-21 01:12:55 -04:00
Domenico Ottolia	bf86a809eb	Add tests for sepc register	2021-04-20 23:50:53 -04:00
Ross Thompson	f3093ac612	Why was the linter messed up? ... There are a number of combo loops which need fixing outside the icache. They may be fixed in main. We get to instruction address 50 now!	2021-04-20 22:06:12 -05:00
Ross Thompson	99424fb983	Progress on icache. Fixed some issues aligning the PC with instruction. Still broken.	2021-04-20 21:19:53 -05:00
Ross Thompson	251ece20fe	Broken icache. Design is done. Time to debug.	2021-04-20 19:55:49 -05:00
Domenico Ottolia	0c307d2db1	Fix synthesis warnings for privileged unit (replace 'initial' settings)	2021-04-20 17:57:56 -04:00
Noah Boorstin	3f0ead9d4e	yay buildroot passes a decent amount of tests now ... gets through the first 15k instructions, that's good enough for now also slight change to string parsing in busybear testbench	2021-04-19 03:26:08 -04:00
Jarred Allen	850f728cc7	Merge branch 'main' into cache	2021-04-19 00:05:23 -04:00
Katherine Parry	d12eb0f4eb	fixed synth bugs in fpu	2021-04-19 00:39:16 +00:00
Noah Boorstin	2af4e2f4ac	slowly more buildroot progress	2021-04-18 18:18:07 -04:00
Noah Boorstin	9bb1233433	neat verilog thing	2021-04-18 17:48:51 -04:00
Noah Boorstin	6954e6df4c	buildroot: sim is now running! ... yes it only gets through 5 instructions right now. Yes that's my fault.	2021-04-17 14:44:32 -04:00
Noah Boorstin	4f97e9e761	start to add buildroot testbench ... This still uses testbench-busybear.sv I think it might be time to finally rename nearly 'busybear' thing to 'linux'	2021-04-16 23:27:29 -04:00
Jarred Allen	aef57cab50	dcache lints	2021-04-15 21:13:56 -04:00
Jarred Allen	7854d838c7	Enable linting of blocks not yet in the hierarchy	2021-04-15 21:13:40 -04:00
bbracker	290b3424e5	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-04-15 21:09:27 -04:00
bbracker	368c94d4ff	working GPIO interrupt demo	2021-04-15 21:09:15 -04:00
Domenico Ottolia	9f13ee3f31	Add tests for scause and ucause	2021-04-15 19:41:25 -04:00
Domenico Ottolia	92bb38fa8c	Add support for vectored interrupts	2021-04-15 19:13:42 -04:00
Domenico Ottolia	eb9e1843fc	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-04-15 16:57:27 -04:00
Domenico Ottolia	531423d7e1	Add 32 bit privileged tests	2021-04-15 16:55:39 -04:00
Teo Ene	2814579f30	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-04-15 15:29:09 -05:00
Teo Ene	374a93dae6	Quick fix to ahblite missing default statement done in class :)	2021-04-15 15:29:04 -05:00
Thomas Fleming	e780694ee0	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/mmu/priority_encoder.sv	2021-04-15 16:20:43 -04:00
Thomas Fleming	6dd7591ceb	Change priority encoder to avoid extra assignment	2021-04-15 16:17:35 -04:00
Thomas Fleming	ff9f1e5e72	Connect tlb and icache properly	2021-04-15 14:48:39 -04:00
Teo Ene	ad86295fcf	Temporary change to mmu/priority_encoder.sv ... Necessary to get synth working Original HDL is still there, just commented out	2021-04-15 13:37:12 -05:00
Katherine Parry	636e2de9df	integraded the FMA into the FPU	2021-04-15 18:28:00 +00:00
Jarred Allen	81c02bda55	Merge branch 'main' into cache	2021-04-15 13:47:19 -04:00
Ross Thompson	87b716170c	Merge branch 'bpfixes' into main	2021-04-15 09:06:21 -05:00
Shreya Sanghai	0369fc5d1e	Cherry Pick merge of Shreya's localhistory predictor changes into main. ... fixed minor bugs in localHistory	2021-04-15 09:04:36 -05:00
ShreyaSanghai	6d4042e479	added localHistoryPredictor	2021-04-15 08:58:22 -05:00
Shreya Sanghai	7e9a0602ea	fixed bugs in global history to read latest GHRE ... Cherry pick Shreya's commits into main branch.	2021-04-15 08:55:22 -05:00
bbracker	e69cc0d23a	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-04-15 09:06:03 -04:00
bbracker	51cdff3e9b	csri lint improvement	2021-04-15 09:05:53 -04:00
Jarred Allen	3717699ad9	Add a comment to explain a detail	2021-04-14 23:14:59 -04:00
Thomas Fleming	3c49fd08f6	Remove imem from testbenches	2021-04-14 20:20:34 -04:00
Jarred Allen	892dfd5a9b	More icache bugfixes	2021-04-14 19:03:33 -04:00
Jarred Allen	c1e2e58ebe	Merge branch 'main' into cache ... Conflicts: wally-pipelined/src/cache/dmapped.sv wally-pipelined/src/cache/line.sv wally-pipelined/src/ifu/icache.sv	2021-04-14 18:24:32 -04:00
bbracker	8f7ddcfdff	rv64 interrupt servicing	2021-04-14 10:19:42 -04:00
Noah Boorstin	d66fcbc4ab	busybear: use (slightly) less terrible verilog	2021-04-14 00:18:44 -04:00
Noah Boorstin	c75455cc41	busybear testbench updates ... start speculative checking on CSR* satp, * add some slight delays in some CSR checkings to make them deterministic I realize this verilog is incredibly un-idiomatic. But I still don't know of anything better. If you figure it out, please let me know	2021-04-14 00:00:27 -04:00
Thomas Fleming	7d2d6823f1	Fix mmu lint errors	2021-04-13 19:19:58 -04:00
Thomas Fleming	0a9b208729	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-04-13 17:15:10 -04:00
Katherine Parry	ef011496a7	Various bugs fixed in FMA	2021-04-13 18:27:13 +00:00
Thomas Fleming	09c9c49541	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/ebu/pagetablewalker.sv	2021-04-13 13:42:03 -04:00
Thomas Fleming	6188f10732	Move InstrPageFault to fetch stage	2021-04-13 13:39:22 -04:00
Thomas Fleming	dc8a165806	Add lru algorithm to TLB	2021-04-13 13:37:24 -04:00
Teo Ene	1018a10625	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
Jarred Allen	4ae1df1290	Merge branch 'main' into cache	2021-04-13 01:10:03 -04:00
Jarred Allen	fc8b8ad7aa	A few more cache fixes	2021-04-13 01:07:40 -04:00
Ross Thompson	35f8b4f74f	Fixed minor bug in muldiv which corrects the lint error.	2021-04-09 10:56:31 -05:00
ushakya22	99f2d24e05	Latest IE tests with timer interupts	2021-04-08 17:53:39 -04:00
Jarred Allen	d99b8f772e	Merge from branch 'main'	2021-04-08 17:19:34 -04:00
Ross Thompson	e73e16e57a	Created special test for driving the instruction spill error. ... The extact problem occurs when a 4 byte instruction startles two cache blocks (or without a cache two ahbi words) and the code jumps to a cache block other than the next cache block. Consider the following sample of code. 0000000000000080 <test_spill>: 80: 42a9 li t0,10 82: 0001 nop 84: 0001 nop 86: 0001 nop 88: 02bd addi t0,t0,15 8a: 00628e33 add t3,t0,t1 8e: 01ce8963 beq t4,t3,a0 <match> 0000000000000092 <failure>: 92: 557d li a0,-1 94: 8082 ret 96: 00000013 nop 9a: 00000013 nop 9e: 0001 nop 00000000000000a0 <match>: a0: 1ffd addi t6,t6,-1 a2: fc0f9fe3 bnez t6,80 <test_spill> a6: 4501 li a0,0 a8: 8082 ret Instructions 0x88, 0x8a and 0x8e are read incorrectly. However once the branch predictor begins to correctly predict the beq at 0x8e the instrution at 0xa0 is loaded incorrectly as the 2 upper bytes of 0x8e and the two bytes of 0x92. This amalgamation causes c.addi at 0xa0 to do something else and the loop never terminates. The button of wavefile wave.do shows the exact problem in the 'icache'.	2021-04-08 15:05:08 -05:00
bbracker	1ee8feffe5	integrated peripheral testing into existing workflow	2021-04-08 15:31:39 -04:00
bbracker	005f838b8d	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-04-08 14:28:25 -04:00
bbracker	755e2e5771	merge testbench	2021-04-08 14:28:01 -04:00
Katherine Parry	b7ebfd66ed	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-04-08 18:06:51 +00:00
David Harris	8549e457c1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-04-08 14:04:09 -04:00
David Harris	6b2868a8c7	restored testbench-imperas.sv	2021-04-08 14:04:01 -04:00
Katherine Parry	2ee015d53e	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-04-08 18:03:57 +00:00
Katherine Parry	f4cb92ae71	fixed FPU lint warnings	2021-04-08 18:03:21 +00:00
Katherine Parry	27cb94e7af	fixed FPU lint warnings	2021-04-08 17:55:25 +00:00
ushakya22	72a64edfb8	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-04-08 13:55:23 -04:00
ushakya22	b0f6898ece	Updates to WALLY-IE tests	2021-04-08 13:54:42 -04:00
David Harris	ac8a111d61	merge conflict resolution	2021-04-08 13:53:56 -04:00
David Harris	6a6ccca3c8	fixed sim-wally-32ic	2021-04-08 13:40:16 -04:00
Noah Boorstin	14d2ad1e2d	try to remove git-lfs stuff	2021-04-08 13:23:11 -04:00
Domenico Ottolia	3067e94b4b	Update privileged testgen & helper script	2021-04-08 05:14:07 -04:00
Domenico Ottolia	65abe13f4f	Cause an Illegal Instruction Exception when attempting to write readonly CSRs	2021-04-08 05:12:54 -04:00
Thomas Fleming	fc39535e4e	Refactor TLB into multiple files	2021-04-08 03:24:10 -04:00
Thomas Fleming	c54aecde73	Provide attribution link for priority encoder	2021-04-08 03:05:06 -04:00
Thomas Fleming	303c2c4839	Implement support for superpages	2021-04-08 02:44:59 -04:00
Ross Thompson	4322694f7a	Switch to use RV64IC for the benchmarks. ... Still not working correctly with the icache. instr addr correct got	2021-04-07 19:12:43 -05:00
ushakya22	83d9aa3a50	MIE privilege tests with working timer interupt	2021-04-07 04:09:09 -04:00
Domenico Ottolia	60cf38192b	Add privileged tests to testbench	2021-04-07 02:22:08 -04:00
Domenico Ottolia	465d3986b0	Add passing mtval and mepc tests	2021-04-07 02:21:05 -04:00
Ross Thompson	c91436d3b7	Merge branch 'icache_bp_bug' into tests ... Not sure this merge is right.	2021-04-06 21:46:40 -05:00
Ross Thompson	98a04abe6c	Merge remote-tracking branch 'refs/remotes/origin/tests' into tests	2021-04-06 21:20:55 -05:00
Ross Thompson	bff2d61a1f	Steps to getting branch predictor benchmarks running.	2021-04-06 21:20:51 -05:00
Jarred Allen	bd8f1eea3c	Fix another bug in icache	2021-04-06 17:47:00 -04:00
Jarred Allen	3afc358974	Fix another bug in icache	2021-04-06 12:48:42 -04:00
Noah Boorstin	284d583877	add busybear boot files with git-lfs	2021-04-05 19:38:43 -04:00
Noah Boorstin	0e3f013212	busybear: reenable 'ruthless' CSR checking	2021-04-05 12:53:30 -04:00
bbracker	38017e6aae	declare memread signal	2021-04-05 08:13:01 -04:00
bbracker	a4c3afb847	PLIC claim reg side effects now check for memread signal	2021-04-05 08:03:14 -04:00
bbracker	4a5aa5b202	plic subword access compliance	2021-04-04 23:10:33 -04:00
Katherine Parry	e6a7353847	Added missing files in FPU	2021-04-04 18:09:13 +00:00
bbracker	31c6b2d01f	Yee hoo first draft of PLIC plus self-checking tests	2021-04-04 06:40:53 -04:00
Thomas Fleming	6b43381c38	Comment out fpu from hart until module exists	2021-04-03 22:34:11 -04:00
Thomas Fleming	dbd5a4320e	Merge branch 'mmu' into main ... Conflicts: wally-pipelined/src/wally/wallypipelinedhart.sv	2021-04-03 22:12:52 -04:00
Thomas Fleming	8dfec29f7e	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-04-03 22:09:50 -04:00
Noah Boorstin	f4e5642c62	busybear: temporary stop after 800k instrs	2021-04-03 21:37:57 -04:00
Thomas Fleming	1cbdaf1f05	Fix extraneous page fault stall	2021-04-03 21:28:24 -04:00
Jarred Allen	c95da7d11e	Fix bug in icache	2021-04-03 18:10:54 -04:00
Katherine Parry	d7b1379ab8	Integrated FPU	2021-04-03 20:52:26 +00:00
Ross Thompson	d21006d048	Partial fix to the integer divide stall issue.	2021-04-02 15:32:15 -05:00
James E. Stine	362f6ea2e6	Minor cleanup	2021-04-02 08:20:44 -05:00
James E. Stine	0595ae983f	Put back imperas testbench until figure out why m_supported is running for rv64ic	2021-04-02 08:19:25 -05:00
James E. Stine	cff08adc3a	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
Thomas Fleming	bfb4b051c6	Merge branch 'main' into mmu	2021-04-01 16:29:39 -04:00
Thomas Fleming	350fe87119	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-04-01 16:24:06 -04:00
Thomas Fleming	38a0199260	Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu	2021-04-01 16:23:19 -04:00
Thomas Fleming	fdb20ee1cf	Implement sfence.vma and fix tlb writing	2021-04-01 15:55:05 -04:00
Jarred Allen	5afb255251	Begin changes to direct-mapped cache	2021-04-01 13:55:21 -04:00
Shreya Sanghai	df149d1be7	fixed minor bugs in localHistory	2021-04-01 13:40:08 -04:00
James E. Stine	0495195d68	Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time.	2021-04-01 12:30:37 -05:00
ShreyaSanghai	28a9c6ba56	added localHistoryPredictor	2021-04-01 22:22:40 +05:30
Shreya Sanghai	b544526766	fixed bugs in global history to read latest GHRE	2021-03-31 21:56:14 -04:00
Teo Ene	7c364a26e9	Updated MISA in coremark_bare config file	2021-03-31 20:39:02 -05:00
Noah Boorstin	75f58c4df5	busybear: temporarially stop checking CSRs	2021-03-31 14:14:32 -04:00
Noah Boorstin	118e846ef7	busybear: clean up questa warnings	2021-03-31 14:04:57 -04:00
Noah Boorstin	43532be770	busybear: clean up questa warnings	2021-03-31 14:02:15 -04:00
Ross Thompson	9172e52286	Corrected a number of bugs in the branch predictor. ... Added performance counters to individually track branches; jumps, jump register, jal, and jalr; return. jump and jump register are special cases of jal and jalr. Similarlly return is a special case of jalr. Also added counters to track if the branch direction was wrong, btb target wrong, or the ras target was wrong. Finally added one more counter to track if the BP incorrectly predicts a non-cfi instruction.	2021-03-31 11:54:02 -05:00
Ross Thompson	a64a37d702	Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.	2021-03-30 23:18:20 -05:00
Thomas Fleming	77b8e27205	Disable 'always-on' virtual memory	2021-03-30 22:49:47 -04:00
Thomas Fleming	56e256baa5	Extend lint-wally to lint both rv32 and rv64	2021-03-30 22:42:28 -04:00
Thomas Fleming	eca2427f94	Merge remote-tracking branch 'origin/main' into main ... Bring icache and MMU code together Conflicts: wally-pipelined/src/ifu/ifu.sv wally-pipelined/testbench/testbench-imperas.sv	2021-03-30 22:24:47 -04:00
Thomas Fleming	7126ab7864	Complete basic page table walker	2021-03-30 22:19:27 -04:00
Thomas Fleming	0994d03b28	Update virtual memory tests and move to separate folder	2021-03-30 22:18:29 -04:00
Domenico Ottolia	f7cbaeb217	Add one more test to WALLY-CAUSE, and update privileged testgen	2021-03-30 19:44:58 -04:00
Domenico Ottolia	6619a5f44f	Add mcause tests to testbench	2021-03-30 17:17:59 -04:00
Domenico Ottolia	61b19a0cd0	Update privileged tests generator	2021-03-30 16:58:46 -04:00
Domenico Ottolia	351c71e812	Add all working mcause tests	2021-03-30 16:55:12 -04:00
ushakya22	6b9ae41302	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
ushakya22	fbed5d658e	privilege tests	2021-03-30 15:23:47 -04:00
Ross Thompson	2a308309e4	fixed some bugs with the RAS.	2021-03-30 13:57:40 -05:00
Jarred Allen	631454ccf9	Merge branch 'cache2' into cache ... Conflicts: wally-pipelined/testbench/testbench-imperas.sv	2021-03-30 13:32:33 -04:00
Jarred Allen	6e83ccc3c4	Comment out failing tests	2021-03-30 13:07:26 -04:00
Jarred Allen	108f18e580	Merge branch 'cache' into main	2021-03-30 12:56:19 -04:00
Jarred Allen	7ca57cc4fc	Merge branch 'main' into cache ... Conflicts: wally-pipelined/regression/wave-dos/ahb-waves.do wally-pipelined/src/ifu/ifu.sv wally-pipelined/testbench/testbench-busybear.sv wally-pipelined/testbench/testbench-imperas.sv	2021-03-30 12:55:01 -04:00
David Harris	8723fb916c	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-26 13:04:52 -04:00
David Harris	637bba6509	Added fp test to testbench	2021-03-26 13:03:23 -04:00
Noah Boorstin	b5a1691c2b	Merge branch 'main' into cache ... Conflicts: wally-pipelined/testbench/testbench-busybear.sv	2021-03-26 12:26:30 -04:00
Shreya Sanghai	339bd5d3eb	Merge branch 'PPA' into main ... Conflicts: wally-pipelined/testbench/testbench-privileged.sv	2021-03-25 20:35:21 -04:00
Shreya Sanghai	cc988f420f	removed minor bugs	2021-03-25 20:29:50 -04:00
Jarred Allen	39bf2347bc	Fix error when reading an instruction that crosses a line boundary	2021-03-25 18:47:23 -04:00
ShreyaSanghai	139c2076a1	Removed PCW and InstrW from ifu	2021-03-26 01:53:19 +05:30
Jarred Allen	32829bf7a1	Remove old icache	2021-03-25 15:46:35 -04:00
Jarred Allen	5f4feb0ff1	Works for misaligned instructions not on line boundaries	2021-03-25 15:42:17 -04:00
Noah Boorstin	05d362e334	regression: use busybear batch instead	2021-03-25 15:34:10 -04:00
Domenico Ottolia	56a32b5882	More bug fixes for privileged tests	2021-03-25 15:05:55 -04:00
Jarred Allen	3b4f0141f4	Begin work on compressed instructions	2021-03-25 14:43:10 -04:00
Noah Boorstin	44060b579b	busybear: quick fix to mem reading ... also stop ignoring mcause at the start	2021-03-25 14:29:11 -04:00
Brett Mathis	162f2df880	FPU Pipeline completed - can begin integration	2021-03-25 13:29:03 -05:00
Domenico Ottolia	f134b09a97	Fix bugs with privileged tests	2021-03-25 14:06:05 -04:00
Noah Boorstin	d02c88dab5	busybear: stop NOPing out atomics ... and bump regression to check for 800k instrs, up from 200k	2021-03-25 13:29:56 -04:00
Jarred Allen	0290568a52	Make cache output NOP after a reset	2021-03-25 13:18:30 -04:00
David Harris	eb9787609e	testgen-PIPELINE python startup	2021-03-25 13:12:18 -04:00
Shriya Nadgauda	21989ee615	adding PIPELINE tests	2021-03-25 13:07:25 -04:00
Jarred Allen	ce6f102fc5	Clean up some stuff	2021-03-25 13:04:54 -04:00
Jarred Allen	128278ea27	Working for all of rv64i now, but not compressed instructions	2021-03-25 13:02:26 -04:00
Jarred Allen	602271ff7b	rv64i linear control flow now working	2021-03-25 13:02:26 -04:00
Jarred Allen	ba95557c44	More progress on icache controller	2021-03-25 13:01:11 -04:00
Jarred Allen	ad0d77e9e1	Begin rewrite of icache module to use a direct-mapped scheme	2021-03-25 13:01:10 -04:00
Jarred Allen	ebd6b931c6	Fix bug in cache line	2021-03-25 12:59:30 -04:00
Jarred Allen	b774d35c34	Output NOP instead of BAD when reset	2021-03-25 12:42:48 -04:00
Jarred Allen	4b92a595ab	Merge branch 'main' into cache ... Conflicts: wally-pipelined/src/uncore/dtim.sv	2021-03-25 12:10:26 -04:00
Teo Ene	51291949d8	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
David Harris	a8abd47fbc	Added PPA README	2021-03-25 11:21:31 -04:00
Thomas Fleming	e3900bd0fa	Finish finite state machines for page table walker	2021-03-25 02:48:40 -04:00
Thomas Fleming	b5003b093a	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-25 02:35:21 -04:00
bbracker	a3788eb218	added 1 tick delay to dtim flops	2021-03-25 02:23:30 -04:00
bbracker	b5fa410e15	added 1 tick delay on tim reads	2021-03-25 02:15:28 -04:00
Jarred Allen	682050a33b	Merge branch 'main' into cache ... Conflicts: wally-pipelined/src/ifu/ifu.sv	2021-03-25 00:51:12 -04:00
bbracker	67b27cd2f5	instrfault direspecting stalls bugfix	2021-03-25 00:44:35 -04:00
bbracker	02e924e55a	instrfaults not respecting stalls bugfix	2021-03-25 00:16:26 -04:00
bbracker	1e3f683a9d	upgraded gpio bus interface	2021-03-25 00:15:02 -04:00
bbracker	e98dd420bc	future work comment about suspicious-looking verilog in csri.sv	2021-03-25 00:10:44 -04:00
Thomas Fleming	b1d849c822	Add all PMP addr registers	2021-03-24 21:58:33 -04:00
Teo Ene	a3aa103dc7	Fix typo from last commit	2021-03-24 17:09:58 -05:00
Teo Ene	4427b5ec01	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-24 17:04:48 -05:00
Teo Ene	e43849b82c	Updated coremark_bare testbench for IM	2021-03-24 17:04:43 -05:00
Katherine Parry	18cb1f4873	fixed various bugs in the FMA	2021-03-24 21:51:17 +00:00
Teo Ene	385ce9a8f9	Added BPTYPE to coremark_bare config	2021-03-24 16:38:29 -05:00
Ross Thompson	a99c0502e5	Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.	2021-03-24 15:56:55 -05:00
Ross Thompson	11109e5a88	Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed.	2021-03-24 13:03:43 -05:00
Domenico Ottolia	d67e28bf50	re-organize privileged tests to be in rv64p to rv32p folders	2021-03-24 13:51:25 -04:00
Jarred Allen	c1fe16b70b	Give some cache mem inputs a better name	2021-03-24 12:31:50 -04:00
Jarred Allen	a51257abca	Fix compile errors from const not actually being constant (why does Verilog do this)	2021-03-24 00:58:56 -04:00
Ross Thompson	1c6e37120e	Fixed RAS errors. Still some room for improvement with the BTB and RAS.	2021-03-23 23:00:44 -05:00
Jarred Allen	4410944049	Merge branch 'main' into cache	2021-03-23 23:35:36 -04:00
Ross Thompson	84ad1353e4	Fixed a bunch of bugs with the RAS.	2021-03-23 21:49:16 -05:00
Katherine Parry	56dc8de009	fixed various bugs in the FMA	2021-03-24 01:35:32 +00:00
Ross Thompson	4fb7a1e0a6	Fixed the valid bit issue. Now the branch predictor is actually predicting instructions.	2021-03-23 20:20:23 -05:00
Ross Thompson	49348d734b	fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle.	2021-03-23 20:06:45 -05:00
Ross Thompson	95dbc5f1fa	fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled.	2021-03-23 16:53:48 -05:00
Jarred Allen	d6ecc3ede0	Begin work on direct-mapped cache	2021-03-23 17:03:02 -04:00
Teo Ene	ef3d2dda48	Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem	2021-03-23 15:21:13 -05:00
Ross Thompson	174557ae89	Simulation definitely shows the branch predictor counters and branch predictor don't work. :(	2021-03-23 14:04:58 -05:00
Ross Thompson	5edc90b1c2	added a whole bunch of interseting test code for branches which does not work.	2021-03-23 13:54:59 -05:00
Ross Thompson	6a050219d4	updated the branch predictor config.	2021-03-23 13:54:59 -05:00
Ross Thompson	9e61481414	Added first benchmark.	2021-03-23 13:54:59 -05:00
Ross Thompson	2b0f7cdd42	Temporary exe2memfile0.pl script to support starting addresses of 0.	2021-03-23 13:54:59 -05:00
Ross Thompson	e1842c8da6	Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses.	2021-03-23 13:54:59 -05:00
Noah Boorstin	69e5319675	busybear: more progress	2021-03-23 14:49:30 -04:00
Shreya Sanghai	1d6a2989ed	PC counts branch instructions	2021-03-23 14:25:51 -04:00
Jarred Allen	0d05c51af9	Remove deleted signal from waves	2021-03-23 14:17:17 -04:00
Noah Boorstin	24e403bc35	busybear: more progress moving from instrf to instrrawd	2021-03-23 14:06:21 -04:00
Noah Boorstin	f3194c6388	busybear: ignore illegal instruction when starting	2021-03-23 13:28:56 -04:00
Jarred Allen	7da8af4c68	Another tweak to regression-wally.py comments	2021-03-23 00:18:38 -04:00
Jarred Allen	0f8fe8fb3b	Document some internal signals	2021-03-23 00:10:35 -04:00
Jarred Allen	6ffa01cc4d	Add comments explaining icache inputs	2021-03-23 00:07:39 -04:00
Jarred Allen	82de84469f	Slight change to regression-wally.py comments	2021-03-23 00:02:40 -04:00
Jarred Allen	827993598d	Small commit to see if new hook tests non-main branch	2021-03-22 23:57:01 -04:00
Noah Boorstin	d5bd5fa9d7	start migrating busybear over to InstrRawD/PCD ... this breaks busybear for now	2021-03-22 23:45:04 -04:00
Noah Boorstin	15474f678d	Merge branch 'main' into cache	2021-03-22 23:28:30 -04:00
Noah Boorstin	849641f31e	busybear: add better warning on illegal instruction ... ...also it seems that mret is being picked up as an illegal instruction??	2021-03-22 18:24:35 -04:00
Noah Boorstin	34b8f750ce	busybear: temporarially force rf[5] correct after failure to read CSR	2021-03-22 18:12:41 -04:00
Noah Boorstin	77dd0b4504	busybear: allow overwriting read values	2021-03-22 17:28:44 -04:00
Noah Boorstin	7bb31c3287	busybear: finally get the right error	2021-03-22 16:52:22 -04:00
bbracker	5efd5958e7	added delays to uart AHB signals	2021-03-22 15:40:29 -04:00
Jarred Allen	6ce52f9b80	Remove DelaySideD since it isn't needed	2021-03-22 15:13:23 -04:00
Jarred Allen	b871bfe714	Update icache interface	2021-03-22 15:04:46 -04:00
Noah Boorstin	2aa76b27e1	busybear: comment out some debug printing	2021-03-22 14:54:05 -04:00
Jarred Allen	3f897bbf53	Merge branch 'main' into cache	2021-03-22 14:50:22 -04:00
Noah Boorstin	74bcd9b994	regression: expect 200k instead of 100k busybear instrs ... and a minor busybear bugfix	2021-03-22 14:47:52 -04:00
Jarred Allen	3748d03adc	Merge branch 'main' into cache	2021-03-22 13:47:48 -04:00
bbracker	11d4a8ab34	first pass at PLIC interface	2021-03-22 10:14:21 -04:00
Katherine Parry	f741ba7702	fixed various bugs in the FMA	2021-03-21 22:53:04 +00:00
Jarred Allen	5b1db9b6a2	Change busybear testbench to reflect new location of InstrF	2021-03-20 18:20:27 -04:00
Jarred Allen	097e8edb3d	Put Imperas testbench back	2021-03-20 18:19:51 -04:00
Jarred Allen	f9cf05a7d4	Fix bug with PC incrementing	2021-03-20 18:06:03 -04:00
Jarred Allen	a3a646d1a9	Merge branch 'main' into cache	2021-03-20 17:56:25 -04:00
Jarred Allen	a2bf5ac202	Fix another bug in the icache (why so many of them?)	2021-03-20 17:54:40 -04:00
Jarred Allen	c5f99c4a34	Revert "Change flop to listen to StallF" ... This reverts commit c8028710a5.	2021-03-20 17:34:19 -04:00
Jarred Allen	b63bfc7afa	Fix conflicts in ahb-waves that snuck through manual merging	2021-03-20 17:16:50 -04:00
Jarred Allen	c8028710a5	Change flop to listen to StallF	2021-03-20 17:04:13 -04:00
Katherine Parry	e317e7511e	messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic	2021-03-20 02:05:16 +00:00
Jarred Allen	279c09b27c	Merge changes from main	2021-03-18 18:58:10 -04:00
Jarred Allen	2a29def21c	Add icache's read request to ahb wavs	2021-03-18 18:52:03 -04:00
bbracker	85363e941d	AHB bugfixes and sim waveview refactoring	2021-03-18 18:25:12 -04:00
bbracker	98e93a63c0	maybe AHB works now	2021-03-18 17:47:00 -04:00
Shreya Sanghai	09faa40eb6	fixed minor bugs in testbench	2021-03-18 17:37:10 -04:00
Shreya Sanghai	bbe0957df5	Merge branch 'gshare' into main ... Conflicts: wally-pipelined/regression/wave.do	2021-03-18 17:25:48 -04:00
Ross Thompson	1091dd10c1	Switched to gshare from global history. ... Fixed a few minor bugs.	2021-03-18 16:05:59 -05:00
Ross Thompson	8f4051543c	Fixed minor bug with the size of gshare.	2021-03-18 16:00:09 -05:00
Shreya Sanghai	eb86bfc084	removed unnecesary PC registers in ifu	2021-03-18 16:31:21 -04:00
Thomas Fleming	8d484174a7	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-18 14:36:42 -04:00
Thomas Fleming	7f7597e667	Connect tlb, pagetablewalker, and memory	2021-03-18 14:35:46 -04:00
Thomas Fleming	7d4906b1c7	Improve page table creation in python file	2021-03-18 14:27:09 -04:00
Noah Boorstin	bc1a0c6ee7	change ifndef to generate/if	2021-03-18 12:50:19 -04:00
Noah Boorstin	a2b0af460e	everyone gets a bootram	2021-03-18 12:35:37 -04:00
Noah Boorstin	ced2a32d21	busybear: update memory map, add GPIO	2021-03-18 12:17:35 -04:00
Teo Ene	57f1ca5259	Switched coremark to RV64IM	2021-03-17 22:39:56 -05:00
Teo Ene	d2fe42d6d0	adapted coremark bare testbench to new dtim RAM HDL	2021-03-17 16:59:02 -05:00
Jarred Allen	e69376c823	Merge branch 'main' into cache ... Conflicts: wally-pipelined/testbench/testbench-imperas.sv	2021-03-17 16:40:52 -04:00
Teo Ene	4fd0ecff69	Temporarily reverted my last few commits	2021-03-17 15:16:01 -05:00
Teo Ene	7446a7b479	fix to last commit	2021-03-17 15:07:02 -05:00
Teo Ene	3e849f99a6	fix to last commit	2021-03-17 15:02:15 -05:00
Teo Ene	d72d774a0b	addition to last commit	2021-03-17 14:52:31 -05:00
Teo Ene	dfe6df2e00	Added Ross's addr lab stuff to coremark stuff	2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg	041439c008	fixing coremark branch prediction	2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg	d0ddb5f461	replicating coremark changes into coremark bare	2021-03-17 14:36:34 -04:00
Elizabeth Hedenberg	da758e9e14	Merge branch '3_3_2021' into main ... Making sure coremark works with spring break changes	2021-03-17 14:11:37 -04:00
Ross Thompson	f070aae847	Fixed issue with sim-wally-batch. Are people still using this script?	2021-03-17 11:17:52 -05:00
Ross Thompson	3618a39087	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-17 11:07:57 -05:00
Ross Thompson	9f8f0242ca	Added possibly working OSU test bench as a precursor to running a bp benchmark. ... Fixed a few bugs with the function radix.	2021-03-17 11:06:32 -05:00
Domenico Ottolia	487b198055	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-16 23:27:09 -04:00
Domenico Ottolia	748372dc45	Add test runner for privileged	2021-03-16 23:26:59 -04:00
Noah Boorstin	bfa7aedd35	busybear: add seperate message on bad memory access becasue its confusing	2021-03-16 21:42:26 -04:00
Noah Boorstin	e7fae21eb8	busybear: add COUNTERS define	2021-03-16 21:08:47 -04:00
Domenico Ottolia	d354cbd37d	Add privileged testbench	2021-03-16 20:28:38 -04:00
Domenico Ottolia	82ea97e304	Add privileged tests for mcause	2021-03-16 19:22:36 -04:00
Domenico Ottolia	1ceb7a7431	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-16 19:12:21 -04:00
Jarred Allen	152ffd16e2	Undo accidental change	2021-03-16 18:16:00 -04:00
Jarred Allen	ae5417195a	Condense the parallel and non-parallel wally-pipelined-batch.do files into one	2021-03-16 18:15:13 -04:00
Jarred Allen	f6cbe44cbd	Change busybear to only check that first 100k instructions load	2021-03-16 17:43:39 -04:00
Shreya Sanghai	36f0631203	added gshare and global history predictor	2021-03-16 17:03:01 -04:00
Jarred Allen	a82aa23399	Fix icache for jumping into misaligned instructions	2021-03-16 16:57:51 -04:00
Domenico Ottolia	b2faf3c888	Add privileged tests folder	2021-03-16 16:11:20 -04:00
Shreya Sanghai	9eed875886	added global history branch predictor	2021-03-16 16:06:40 -04:00
Jarred Allen	2d2092e8ab	Merge remote-tracking branch 'origin/main' into cache	2021-03-16 14:17:39 -04:00
Shreya Sanghai	08e9149e20	made performance counters count branch misprediction	2021-03-16 11:24:17 -04:00
Shreya Sanghai	74f1641c5a	Merge branch 'counters' into main ... added a configurable number of performance counters	2021-03-16 11:01:30 -04:00
Jarred Allen	36452749d7	Merge remote-tracking branch 'origin/main' into cache	2021-03-15 19:08:25 -04:00
Noah Boorstin	9e1612c166	remove regression-wally.sh	2021-03-15 19:03:57 -04:00
Noah Boorstin	400791163e	copy Ross's branch predictor preload change into busybear	2021-03-15 18:27:27 -04:00
Ross Thompson	4c8952de6a	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
Ross Thompson	f2a6e8c6cf	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main ... The last commit message about rv32ic having issues is now invalid. Looks like the issue was resolved.	2021-03-15 12:06:18 -05:00
Ross Thompson	806cfc4ea5	Fixed the parallel script so the rv64ic passes. ... rv32ic and busybear still have issues.	2021-03-15 12:04:59 -05:00
Jarred Allen	ac9fd5a323	Fix BEQZ tests	2021-03-14 15:42:27 -04:00
Jarred Allen	926235b180	Merge upstream changes	2021-03-14 14:57:53 -04:00
Jarred Allen	deb13f34bb	Get non-jump case working	2021-03-14 14:46:21 -04:00
bbracker	e58d17d5b7	slightly smarter dtim HREADY	2021-03-13 07:03:33 -05:00
bbracker	345254b5a3	slightly smarter dtim HREADY	2021-03-13 06:55:34 -05:00
bbracker	c5015e5809	imem rd2 adrbits bugfix	2021-03-13 00:10:41 -05:00
Ross Thompson	940d892f29	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-12 20:18:35 -06:00
Ross Thompson	7ceef2b0c6	Fixed the issue with the batch mode not working after adding the function radix.	2021-03-12 20:16:03 -06:00
bbracker	f4fb546969	clint HREADY signal update	2021-03-12 20:23:55 -05:00
Ross Thompson	86078d856f	Cleaned up the function radix exractFunctionRadix script. I should change the name as this is no longer a modelsim radix.	2021-03-12 15:29:02 -06:00
Ross Thompson	6ee97830f7	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-12 14:58:04 -06:00
Ross Thompson	7743d8edc3	Cleanup of the branch predictor flush and stall controls.	2021-03-12 14:57:53 -06:00
David Harris	56b690ccb9	Drafted rv32a tests	2021-03-12 00:06:23 -05:00
David Harris	865c103599	64-bit AMO debugged	2021-03-11 23:18:33 -05:00
Ross Thompson	318b642359	Improve version of the function radix which does not cause the wave file rendering to slow down.	2021-03-11 17:12:21 -06:00
Noah Boorstin	cc94046084	test regression script: add commented out rv32ic tests	2021-03-11 12:57:54 -05:00
Noah Boorstin	394b79b5de	add rv32ic regression test	2021-03-11 12:40:29 -05:00
Noah Boorstin	54fa16d783	test regression script: parallalize better	2021-03-11 12:25:20 -05:00
Noah Boorstin	aba54659bf	test regression script: try adding verilator checking also	2021-03-11 07:32:31 +00:00
Noah Boorstin	81c14f899d	try adding delays to test regression script	2021-03-11 06:59:50 +00:00
Noah Boorstin	1093b07670	this is just a test for now, try to reimplement regression-wally in bash	2021-03-11 06:45:45 +00:00
Noah Boorstin	a8b242a6ef	busybear: account for CSR moving	2021-03-11 06:45:14 +00:00
Thomas Fleming	1294235837	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/ebu/ahblite.sv	2021-03-11 00:15:58 -05:00
David Harris	42275e92ed	Initial untested implementation of AMO instructions	2021-03-11 00:11:31 -05:00
Jarred Allen	4757794887	Return testbench to normal	2021-03-10 22:58:41 -05:00
Ross Thompson	845115302e	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-10 15:37:02 -06:00
Ross Thompson	f92f766573	Added debug option to disable the function radix if not needed. ... Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.	2021-03-10 15:17:02 -06:00
Ross Thompson	dcae90e3ad	I finally think I got the function radix debugger working across both 32 and 64 bit applications.	2021-03-10 14:43:44 -06:00
Noah Boorstin	2c25e270a2	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
Ross Thompson	50a92247b3	Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand.	2021-03-10 11:00:51 -06:00
Jarred Allen	ae9bcc174d	Merge upstream changes	2021-03-09 21:20:34 -05:00
Jarred Allen	3172be3039	More progress	2021-03-09 21:16:07 -05:00
David Harris	c2f340681d	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-09 09:28:32 -05:00
David Harris	17c0f9629a	WALLY-LRSC atomic test passing	2021-03-09 09:28:25 -05:00
Noah Boorstin	4a8b689f62	busybear: better NOPing out of float instructions	2021-03-08 21:24:19 +00:00
Noah Boorstin	c780a25f92	busybear: better instrF checking ... So this now checks instrF only when StallD is low. @kaveh I'd love your opinion on this. I don't know if this is a good idea or not. Ideally we should probably be checking InstrRawD instead, but I kind of want to stay checking the instr in the F stage instead of D for now. Idk if this is worth staying in F, I can't really see any big downsides to checking the instruction in D except that PCD isn't an external signal, but neither is StallD, so..... Anyway I'd love others' thoughts on this	2021-03-08 19:48:12 +00:00
Noah Boorstin	1b206d5a3c	busybear: make a second .do file with better optimization for command line mode	2021-03-08 19:35:00 +00:00
Noah Boorstin	93c9c57426	busybear: load mem files from verilog instead of .do	2021-03-08 19:26:26 +00:00
David Harris	9c7da510fb	Created atomic test vector and directories	2021-03-08 09:38:55 -05:00
Ross Thompson	d5f151eb0f	Updated the paths to the branch predictor memory preloads for busy bear.	2021-03-05 15:36:00 -06:00
Ross Thompson	87ed6d510c	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-05 15:27:22 -06:00
Ross Thompson	301166d062	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
Thomas Fleming	2b891196d9	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-05 16:20:53 -05:00
Noah Boorstin	3c5be59e9b	busybear: add branch preditor loading to do file ... (sorry to add more loading to the do instead of less)	2021-03-05 21:01:41 +00:00
Thomas Fleming	be6ee84d87	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-05 15:46:51 -05:00
Noah Boorstin	86142e764a	Merge branch 'main' into busybear	2021-03-05 20:27:19 +00:00
Noah Boorstin	889d2c0b85	fix wally-pipelined-batch.do to match wally-pipelined.do	2021-03-05 20:27:01 +00:00
bbracker	850a2e9329	added a delay to sel signals	2021-03-05 15:07:34 -05:00
bbracker	77e2e357a7	more merging fixes	2021-03-05 14:36:07 -05:00
bbracker	ed4ff1ecd0	remove deprecated mem signals	2021-03-05 14:27:38 -05:00
bbracker	19fc7d2381	refactored sim file	2021-03-05 14:25:16 -05:00
bbracker	0f4a231543	first merge of ahb fix	2021-03-05 14:24:22 -05:00
Noah Boorstin	1a11b60664	busybear: slight testbench update	2021-03-05 19:00:40 +00:00
Thomas Fleming	2e2eb5839f	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-05 13:35:44 -05:00
Thomas Fleming	8c97143be6	Place tlb parameters into constant header file	2021-03-05 13:35:24 -05:00
Thomas Fleming	7e11317a2d	Export SATP_REGW from csrs to MMU modules	2021-03-05 01:22:53 -05:00
Noah Boorstin	f48af209c4	busybear: make CSRs only weird for us	2021-03-05 00:46:32 +00:00
Noah Boorstin	5a3ba1174e	busybear: better implenetation of sim-busybear-batch	2021-03-05 00:39:03 +00:00
Ross Thompson	a662aa487c	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-04 17:31:27 -06:00
Ross Thompson	264480f258	updated the function radix to look at wally signals.	2021-03-04 17:31:12 -06:00
Jarred Allen	41f682f848	Partial progress towards compressed instructions	2021-03-04 18:30:26 -05:00
Noah Boorstin	dfae278ffb	busybear: make imperas tests work again	2021-03-04 22:44:49 +00:00
Katherine Parry	cfac6bf0c7	fixed various bugs	2021-03-04 22:20:39 +00:00
Katherine Parry	09564f1c77	fixed various bugs	2021-03-04 22:20:28 +00:00
Katherine Parry	a6bc39b5ad	fixed various bugs	2021-03-04 22:20:23 +00:00
Katherine Parry	526e3f5996	fixed various bugs	2021-03-04 22:20:02 +00:00
Katherine Parry	1e906b36a0	fixed various bugs	2021-03-04 22:19:21 +00:00
Katherine Parry	3fb0f323b8	fixed various bugs	2021-03-04 22:18:47 +00:00
Katherine Parry	fdfc0dbf46	fixed various bugs	2021-03-04 22:18:19 +00:00
Jarred Allen	106718b196	Remove rd2, working for non-compressed	2021-03-04 16:46:43 -05:00
Thomas Fleming	3303a013ef	Merge branch 'walker' into main	2021-03-04 15:27:03 -05:00
Noah Boorstin	735c6789ea	busybear: comment out instraccessfaultf for imem for now	2021-03-04 20:26:41 +00:00
Noah Boorstin	827dfd774b	Merge branch 'main' into busybear ... Conflicts: wally-pipelined/src/uncore/imem.sv	2021-03-04 20:16:03 +00:00
Ross Thompson	66e84f3a2c	Merge branch 'bp' into main ... Concerns: 1. I don't think the correct data buses are going to the multiplier. 2. I'm not sure the FlushF signal is correct.	2021-03-04 13:35:46 -06:00
Ross Thompson	4d14c714a7	Fixed forwarding around the 2 bit predictor.	2021-03-04 13:01:41 -06:00
Shreya Sanghai	246dbd05e7	fixed bugs	2021-03-04 12:59:45 -05:00
Shreya Sanghai	f0ec365117	added performance counters	2021-03-04 11:42:52 -05:00
bbracker	448cba2a5b	JALR testing	2021-03-04 10:37:30 -05:00
Ross Thompson	52d95d415f	Converted to using the BTB to predict the instruction class.	2021-03-04 09:23:35 -06:00
Teo Ene	06be82fc67	Added stop to coremark_bare testbench	2021-03-04 07:47:07 -06:00
Teo Ene	8f1584ca04	Edited assemby of bare-metal coremark to make it run	2021-03-04 07:45:40 -06:00
Teo Ene	396dc61564	Linux CoreMark and baremetal CoreMark split into two separate tests/configs	2021-03-04 07:44:33 -06:00
Teo Ene	6ebb79abe0	Linux CoreMark is operational	2021-03-04 05:58:18 -06:00
Thomas Fleming	de3f2547f4	Install dtlb in dmem	2021-03-04 03:30:06 -05:00
Thomas Fleming	1df7151fb6	Install tlb into ifu	2021-03-04 03:11:34 -05:00
Thomas Fleming	2e409f2299	Merge branch 'tlb_toy' into main	2021-03-04 02:41:11 -05:00
Thomas Fleming	5f98c932bf	Move tlb into mmu directory	2021-03-04 02:39:08 -05:00
Teo Ene	f060f6cb9d	Fix to 32-bit option of commit babe6ce9db	2021-03-04 01:33:34 -06:00
Teo Ene	08a7f6ec25	In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches	2021-03-04 01:27:05 -06:00
Thomas Fleming	d9f396ee0e	Merge branch 'main' into tlb_toy	2021-03-04 01:18:04 -05:00
Thomas Fleming	347275e7ee	Generalize tlb module ... - number of tlb entries is now parameterized - tlb now supports rv64i	2021-03-04 01:13:31 -05:00
Teo Ene	6031269de8	Implemented fix disucssed with Elizabeth	2021-03-03 18:17:53 -06:00
Thomas Fleming	394051c02f	Begin hardware page table walker	2021-03-03 17:13:45 -05:00
Thomas Fleming	d8ac9034b7	Create virtual memory ad-hoc test ... Test program is currently failing on ovpsim. There is no indication that ovpsim is properly implementing virtual memory translation when satp is set accordingly. Need to confirm whether this is a problem with ovpsim, how ovpsim is being called, or the test itself.	2021-03-03 17:06:37 -05:00
Teo Ene	4562c61af3	Fix to last push	2021-03-03 15:20:38 -06:00
Teo Ene	37bf3d836f	Updated coremark .do file for easier debugging	2021-03-03 15:10:39 -06:00
Teo Ene	e6044b9867	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-02 17:23:44 -06:00
Teo Ene	e7f7f980b3	Updated coremark .do file for easier debugging	2021-03-02 17:23:39 -06:00
Noah Boorstin	21b1c4163c	busybear: add sim-busybear and sim-busybear-batch based on sim-wally	2021-03-01 21:01:15 +00:00
Noah Boorstin	62b441f3f5	busybear: probably discovered bug in ahb code	2021-03-01 20:56:04 +00:00
Noah Boorstin	965d48afe7	busybear: only check pc when it actually changes	2021-03-01 19:08:35 +00:00
Noah Boorstin	4833b36535	busybear: more adapting to new memory system	2021-03-01 18:50:42 +00:00
Noah Boorstin	26d4024b33	busybear: fix bootram range	2021-03-01 17:45:21 +00:00
David Harris	9bcddfa5dd	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-01 00:09:55 -05:00
David Harris	2543c29839	Initial (untested) implementation of lr and sc	2021-03-01 00:09:45 -05:00
Teo Ene	babe6ce9db	Properly implemented the fix from commit 31c07b2adc	2021-02-28 22:22:04 -06:00
Noah Boorstin	bcc0010498	Merge branch 'main' into busybear	2021-02-28 20:45:08 +00:00
Noah Boorstin	f306d2d2e1	busybear: start preloading bootmem	2021-02-28 20:43:57 +00:00
Noah Boorstin	db86d20d11	busybear: check instead of providing InstrF	2021-02-28 16:46:53 +00:00
Noah Boorstin	a03796a519	busybear: change sstatus, mstatus reset value	2021-02-28 16:19:03 +00:00
Noah Boorstin	6e70ae8b3d	busybear: add 2nd dtim for bootram	2021-02-28 16:08:54 +00:00
Noah Boorstin	edd5e9106d	busybear: remove gpio, start adding 2nd ram	2021-02-28 06:02:40 +00:00
Noah Boorstin	e5e345d161	busybear: instantiate normal wallypipelinedsoc	2021-02-28 06:02:21 +00:00
Ross Thompson	7592a0dacb	Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.	2021-02-26 20:12:27 -06:00
Ross Thompson	37e6a45d76	Updating the test bench to include a function radix. Not done.	2021-02-26 19:43:40 -06:00
David Harris	cf03afa880	Eliminated flushing pipeline on CSR reads	2021-02-26 17:00:07 -05:00
David Harris	015b632eb1	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
kaveh pezeshki	c7863d58cd	merged with main to integrate with AHB	2021-02-26 05:37:10 -08:00
Noah Boorstin	ab9247d625	busybear: add main ram loading, better instr checking also	2021-02-26 20:26:54 +00:00
kaveh Pezeshki	ad631ec3a1	fixed sensitivity list on error checking always block, removed useless once and for all	2021-02-26 13:41:16 -05:00
kaveh pezeshki	d32421822c	restored	2021-02-26 02:22:08 -08:00
David Harris	b16846bddb	Clean up bus interface code	2021-02-26 01:03:47 -05:00
David Harris	24f767a404	Retimed peripherals for AHB interface	2021-02-26 00:55:41 -05:00
David Harris	c060e427f0	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-25 15:49:38 -05:00
David Harris	a16fd95eed	Restored to working multiplier after Lab 2	2021-02-25 15:32:43 -05:00
Brett Mathis	ec82453ba1	FPU Assembly tests	2021-02-25 14:32:36 -06:00
Teo Ene	6be5bb1f84	Fixed previous commit	2021-02-25 11:24:44 -06:00
Teo Ene	31c07b2adc	Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now.	2021-02-25 11:23:01 -06:00
Teo Ene	61b872a3e8	Changed TIMBASE in coremark config file	2021-02-25 11:03:41 -06:00
Teo Ene	c47872c2af	Changed .do file back to run all	2021-02-25 09:58:54 -06:00
David Harris	d00d42cf9a	Merged bus into main	2021-02-25 00:28:41 -05:00
Teo Ene	3e5de35fc4	Added provisional coremark files from work with Elizabeth	2021-02-24 20:07:07 -06:00
kaveh pezeshki	3bb8e0d918	condensed always blocks to avoid race conditions	2021-02-24 11:35:28 -08:00
Noah Boorstin	3d82ceffb7	busybear: preload bootram ... thanks to Prof Stine for the .do file commands @kaveh can you check line 201? it does nothing, but things break when I remove that line	2021-02-24 18:46:09 +00:00
David Harris	f5e9c91193	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
kaveh pezeshki	b36a5614b4	added comments for RAM and bootram, removed trailing whitepace	2021-02-23 21:28:33 -08:00
Noah Boorstin	c8e9edcc43	busybear: add bootram section in the same manner as ram	2021-02-24 02:02:28 +00:00
Noah Boorstin	a24270c4ca	busybear: add support for subwords in ram ... this is really weird and i'm not sure if i did it right. I'd love if @kaveh could review it	2021-02-24 01:51:18 +00:00
Noah Boorstin	00605864fc	busybear: start adding ram	2021-02-23 22:01:23 +00:00
Katherine Parry	8f5cc19143	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-23 20:21:53 +00:00
Katherine Parry	7b103423e1	inital FMA push	2021-02-23 20:19:12 +00:00
Noah Boorstin	d5e7a8a4cf	busybear: remove unused signals	2021-02-23 19:38:19 +00:00
Noah Boorstin	ceb7df3561	busybear: instantiate soc instead of hart	2021-02-23 18:59:06 +00:00
David Harris	c52a99ce2d	Fixed fetch stall after jump in bus unit	2021-02-23 09:08:57 -05:00
David Harris	817f81c356	Debugging Bus interface	2021-02-22 13:48:30 -05:00
kaveh pezeshki	62d9185212	Merge remote-tracking branch 'origin/tlb_toy' into busybear	2021-02-22 02:23:01 -08:00
Ross Thompson	9b3637bd87	RAS needs to be reset or preloaded. For now I just reset it. ... Fixed bug with the instruction class. Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.	2021-02-19 20:09:07 -06:00
Ross Thompson	00de91cc87	Added FlushF to hazard unit. ... Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.	2021-02-19 16:36:51 -06:00
Ross Thompson	f25de68b7d	minor change to wave file.	2021-02-19 09:08:13 -06:00
Ross Thompson	c6ebe7733b	Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. ... About 149307ns of simulation run.	2021-02-18 21:32:15 -06:00
Thomas Fleming	21552eaf9d	Create simple TLB ... This TLB is just a demonstration and is not currently instantiated by the IFU or DFU.	2021-02-18 18:06:09 -05:00
David Harris	acd7ba8b60	Updated creation date of mul	2021-02-18 08:13:08 -05:00
Ross Thompson	de9e383bc6	Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables. ... Once combined with some simulation verilog this will display the current function in modelsim.	2021-02-17 22:20:28 -06:00
Ross Thompson	5df7e959f3	Integrated the branch predictor into the hardward. Not yet working.	2021-02-17 22:19:17 -06:00
David Harris	2f5b4c3a25	Resotred part of multiplier for lab 2	2021-02-17 16:14:04 -05:00
David Harris	64536dbc34	Removed multiplier for lab 2	2021-02-17 16:06:16 -05:00
David Harris	dc758a0c7b	Multiplier tweaks	2021-02-17 16:00:27 -05:00
David Harris	3edf910c18	Started to integrate OSU divider	2021-02-17 15:38:44 -05:00
David Harris	cb0054b524	Multiply instructions working	2021-02-17 15:29:20 -05:00
Noah Boorstin	5835641c6c	busybear testbench: check (almost) all the CSRs	2021-02-16 20:03:24 -05:00
David Harris	8dec69c2ce	Added MUL	2021-02-15 22:27:35 -05:00
Ross Thompson	78db3654c6	We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS. ... This is not yet tested but the system verilog does compile.	2021-02-15 14:51:39 -06:00
David Harris	f00728448a	WALLY ALU tests	2021-02-15 10:16:31 -05:00
David Harris	37dba8fd26	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
Domenico Ottolia	75d9091fe8	Add privileged test cases	2021-02-14 17:01:46 -05:00
Ross Thompson	3ec1f668fc	added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior.	2021-02-14 15:13:55 -06:00
Ross Thompson	30df1cdd25	The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables.	2021-02-14 11:06:31 -06:00
Shreya Sanghai	30bfd7534c	added branch tests	2021-02-12 22:40:08 -05:00
Noah Boorstin	7312da1a99	busybear: allow testbench to ignore lack of MMU for now ... I'd really like to go over this with someone else, not sure if this is a good thing to be doing If it is, we're at 1M instructions!	2021-02-12 20:08:56 +00:00
Noah Boorstin	97302dd12f	busybear: slightly neater error handling	2021-02-12 17:21:56 +00:00
bbracker	9231646fb3	bus rw bugfix and peripherals testing	2021-02-12 00:02:45 -05:00
Noah Boorstin	5bf6add635	bump into virtual/physcial memory?	2021-02-11 23:06:12 -05:00
Noah Boorstin	4427780a41	busybear: more updates ... now gets to instruction 839037 before failing also updates to match new gdb output format umm there seems to be something wrong with the SSTATUS CSR. Just leaving it out for now, will come back and check it later	2021-02-11 22:42:58 -05:00
Tejus Rao	5158ca4220	added test cases for ADDW, SUBW, SLLW, SRLW, SRAW	2021-02-11 13:38:38 -05:00
Teo Ene	8a6de4fb86	Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts	2021-02-10 20:48:39 -06:00
ethan-falicov	9edc4b6bfe	Fixed merge conflict stuff	2021-02-10 10:03:30 -05:00
ethan-falicov	7e8a58de1a	More merge conflicts yay	2021-02-10 09:54:30 -05:00
ethan-falicov	f778f464b7	Merge conflict fixing	2021-02-10 09:45:47 -05:00
ethan-falicov	06541260e0	Adding I Type test cases from Lab 1	2021-02-10 09:39:43 -05:00
David Harris	183a2dcfb5	Debugging bus interface.	2021-02-10 01:43:54 -05:00
David Harris	2357f5513b	Debugging instruction fetch	2021-02-09 11:02:17 -05:00
David Harris	63c7c18771	Fixed lw by delaying read value by one cycle	2021-02-07 23:28:21 -05:00
David Harris	3551cc859b	Data memory bus integration	2021-02-07 23:21:55 -05:00
Jarred Allen	403a0d033c	Fix compile error in imperas testbench	2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg	81a1eb9a74	merge conflict?	2021-02-07 02:34:49 -05:00
Noah Boorstin	01c0f9db63	Busybear: next week of updates ... - move parsed instructions out of git, to /courses/e190ax/busybear_boot - parsed first 1M instructions, and now parse from split GDB runs - now at about 230k instructions, can't progress further for now since atomic instructions aren't implemented yet	2021-02-07 03:14:48 +00:00
Jarred Allen	48ade25577	Actually run the WALLY-LOAD tests	2021-02-06 14:56:40 -05:00
Jarred Allen	edd758453e	Add test vector set for load instructions	2021-02-06 13:05:59 -05:00
bbracker	691d651fde	JAL testing	2021-02-05 08:08:42 -05:00
Noah Boorstin	14cde0d59c	Change CSR reset and available bits to conform to OVPsim ... Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.	2021-02-04 22:03:45 +00:00
Thomas Fleming	8588a1ed6b	Complete STORE tests	2021-02-04 15:38:22 -05:00
Noah Boorstin	dc881bd51b	busybear: add more CSRs	2021-02-04 20:13:36 +00:00
Noah Boorstin	d9431d5bed	busybear: check initial values also	2021-02-04 19:22:09 +00:00
Brett Mathis	79cb7ed571	Parallel FSR's and F CTRL logic	2021-02-04 02:25:55 -06:00
Jarred Allen	ea791cb057	Change busybear test to use work-busybear library	2021-02-03 11:12:47 -05:00
Jarred Allen	743695400d	Start on a test set for loads	2021-02-03 00:37:43 -05:00
David Harris	91f6858de7	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-02 19:44:43 -05:00