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read from MSTATUS workaround because QEMU has incorrect MSTATUS

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bbracker 2021-06-20 10:11:39 -04:00
parent 14ae87ff0a
commit 2643130c41
2 changed files with 6 additions and 3 deletions
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2
wally-pipelined/regression/regression-wally.py
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@ -31,7 +31,7 @@ configs = [
TestCase(
name="buildroot",
cmd="vsim -do wally-buildroot-batch.do -c > {}",
grepstr="# loaded 600000 instructions"
grepstr="# loaded 2000000 instructions"
),
TestCase(
name="rv32ic",

7
wally-pipelined/testbench/testbench-linux.sv
View File

@ -49,7 +49,7 @@ module testbench();
logic ignoreRFwrite;
parameter waveOnICount = 690000; // # of instructions at which to turn on waves in graphical sim
parameter waveOnICount = 2060000; // # of instructions at which to turn on waves in graphical sim
assign GPIOPinsIn = 0;
assign UARTSin = 1;
@ -498,6 +498,9 @@ module testbench();
scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected);
scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
force dut.hart.ieu.dp.regf.wd3 = regExpected;
// Hack to compensate for QEMU's incorrect MSTATUS
end else if (PCtextW.substr(0,3) == "csrr" && PCtextW.substr(10,16) == "mstatus") begin
force dut.hart.ieu.dp.regf.wd3 = dut.hart.ieu.dp.WriteDataW & ~64'ha00000000;
end else
release dut.hart.ieu.dp.regf.wd3;
end
@ -590,7 +593,7 @@ module testbench();
scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) ||
(instrs <= 1000 && instrs % 100 == 0) || (instrs <= 10000 && instrs % 1000 == 0) ||
(instrs <= 100000 && instrs % 10000 == 0) || (instrs <= 1000000 && instrs % 100000 == 0)) begin
(instrs <= 100000 && instrs % 10000 == 0) || (instrs % 100000 == 0)) begin
$display("loaded %0d instructions", instrs);
end
if (instrs == waveOnICount) begin