forked from Github_Repos/cvw
still not sure if QEMU workaround is correct, but here is all linux progress so far
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bbracker
parent
e41a87be23
commit
6625f74a85
4
.gitignore
vendored
4
.gitignore
vendored
@ -16,8 +16,8 @@ wlft*
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/imperas-riscv-tests/FunctionRadix.addr
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/imperas-riscv-tests/ProgramMap.txt
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/imperas-riscv-tests/logs
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/wally-pipelined/busybear-testgen/gdbcombined.txt
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/wally-pipelined/busybear-testgen/first10.txt
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/wally-pipelined/linux-testgen/qemu_output.txt
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/wally-pipelined/linux-testgen/qemu_in_gdb_format.txt
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*.o
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*.d
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testsBP/*/*/*.elf*
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@ -2,25 +2,26 @@
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# Uncomment this version for GDB/QEMU debugging
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# - Opens up GDB interactively
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# - Logs raw QEMU output to qemu_output.txt
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#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2> /mnt/scratch/wally_linux_output/qemu_output.txt) & riscv64-unknown-elf-gdb
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#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2> qemu_output.txt) & riscv64-unknown-elf-gdb
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# Uncomment this version to generate qemu_output.txt
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# - Uses GDB script
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# - Logs raw QEMU output to qemu_output.txt
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#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>/mnt/scratch/wally_linux_output/qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_qemulog
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#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_qemulog_debug
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# Uncomment this version for parse_qemu.py debugging
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# - Uses qemu_output.txt
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# - Makes qemu_in_gdb_format.txt
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# - Logs parse_qemu.py's simulated gdb output to qemu_in_gdb_format.txt
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#cat /mnt/scratch/wally_linux_output/qemu_output.txt | ./parse_qemu.py >/mnt/scratch/wally_linux_output/qemu_in_gdb_format.txt
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#cat qemu_output.txt | ./parse_qemu.py >qemu_in_gdb_format.txt
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#cat qemu_output.txt | ./parse_qemu.py | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/"
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# Uncomment this version for parse_gdb_output.py debugging
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# - Uses qemu_in_gdb_format.txt
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# - Logs info needed by buildroot testbench
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cat /mnt/scratch/wally_linux_output/qemu_in_gdb_format.txt | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/"
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#cat qemu_in_gdb_format.txt | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/"
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# =========== Just Do the Thing ==========
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# Uncomment this version for the whole thing (if it works ha ha_
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# Uncomment this version for the whole thing
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# - Logs info needed by buildroot testbench
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#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>&1 >/dev/null | pv -l | ./parse_qemu.py | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/") & riscv64-unknown-elf-gdb -x gdbinit_qemulog
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(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>&1 >/dev/null | pv -l | ./parse_qemu.py | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/") & riscv64-unknown-elf-gdb -x gdbinit_qemulog
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@ -27,7 +27,7 @@ try:
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readType = ''
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lastReadType = ''
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readLoc = ''
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instrStart = -1
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lineOffset = -1
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lastRegs = ''
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curRegs = ''
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storeReg = ''
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@ -40,10 +40,12 @@ try:
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for l in fileinput.input('-'):
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l = l.split("#")[0].rstrip()
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if l.startswith('=>'):
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# Begin new instruction
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instrs += 1
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storeAMO = ''
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if instrs % 10000 == 0:
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print(instrs)
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# Instr in human assembly
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wPC.write('{} ***\n'.format(' '.join(l.split(':')[1].split()[0:2])))
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if '\tld' in l or '\tlw' in l or '\tlh' in l or '\tlb' in l:
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currentRead = l.split()[-1].split(',')[0]
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@ -53,7 +55,6 @@ try:
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readLoc = l.split()[-1].split(',')[1].split('(')[1][:-1]
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readType = l.split()[-2]
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if 'amo' in l:
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#print(l)
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currentRead = l.split()[-1].split(',')[0]
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readOffset = "0"
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readLoc = l.split()[-1].split('(')[1][:-1]
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@ -63,7 +64,6 @@ try:
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storeReg = l.split()[-1].split(',')[1]
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storeAMO = l.split()[-2]
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if '\tsd' in l or '\tsw' in l or '\tsh' in l or '\tsb' in l:
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#print(l)
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s = l.split('#')[0].split()[-1]
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storeReg = s.split(',')[0]
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if len(s.split(',')) < 2:
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@ -74,17 +74,19 @@ try:
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print(l)
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storeOffset = s.split(',')[1].split('(')[0]
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storeLoc = s.split(',')[1].split('(')[1][:-1]
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instrStart = 0
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elif instrStart != -1:
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instrStart += 1
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if instrStart == 1:
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lineOffset = 0
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elif lineOffset != -1:
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lineOffset += 1
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if lineOffset == 1:
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# Instr in hex comes one line after the instruction
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wPC.write('{}\n'.format(l.split()[-1][2:]))
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elif instrStart < 34:
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# As well as instr address
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wPC.write('{}\n'.format(l.split()[0][2:].strip(":")))
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elif lineOffset <= (1+32):
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# Next 32 lines are the Register File
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if lastRead == l.split()[0]:
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readData = int(l.split()[1][2:], 16)
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readData <<= (8 * (lastReadLoc % 8))
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#if(lastReadLoc % 8 != 0 and ('lw' in lastReadType or 'lb' in lastReadType)):
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# readData <<= 32
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wMem.write('{:x}\n'.format(readData))
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if readLoc == l.split()[0]:
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readLoc = l.split()[1][2:]
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@ -92,16 +94,12 @@ try:
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storeReg = l.split()[1]
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if storeLoc == l.split()[0]:
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storeLoc = l.split()[1][2:]
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if instrStart > 2:
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#print(l)
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#print(instrStart)
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if lineOffset > (1+1):
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# Start logging x1 onwards (we don't care about x0)
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curRegs += '{}\n'.format(l.split()[1][2:])
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elif instrStart < 35:
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#print("----------")
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#print(l.split()[1][2:])
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wPC.write('{}\n'.format(l.split()[1][2:]))
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#print(l.split()[1][2:])
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if any([c == l.split()[0] for c in csrs]):
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#elif "pc" in l:
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# wPC.write('{}\n'.format(l.split()[1][2:]))
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if any([csr == l.split()[0] for csr in csrs]):
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if l.split()[0] in curCSRs:
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if curCSRs[l.split()[0]] != l.split()[1]:
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if firstCSR:
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@ -112,51 +110,53 @@ try:
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wCSRs.write('{}\n{}\n'.format(l.split()[0], l.split()[1][2:]))
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curCSRs[l.split()[0]] = l.split()[1]
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if '-----' in l: # end of each cycle
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if curRegs != lastRegs:
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if lastRegs == '':
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wReg.write(curRegs)
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else:
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for i in range(32):
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if curRegs.split('\n')[i] != lastRegs.split('\n')[i]:
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wReg.write('{}\n'.format(i+1))
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wReg.write('{}\n'.format(curRegs.split('\n')[i]))
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break
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lastRegs = curRegs
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if lastAMO != '':
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if 'amoadd' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16) + readData)[2:]
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elif 'amoand' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16) & readData)[2:]
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elif 'amoor' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16) | readData)[2:]
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elif 'amoswap' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16))[2:]
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else:
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print(lastAMO)
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exit()
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wMemW.write('{}\n'.format(lastStoreReg))
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wMemW.write('{:x}\n'.format(int(lastStoreLoc, 16)))
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if storeReg != '' and storeOffset != '' and storeLoc != '' and storeAMO == '':
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storeLocOffset = int(storeOffset,10) + int(storeLoc, 16)
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#wMemW.write('{:x}\n'.format(int(storeReg, 16) << (8 * (storeLocOffset % 8))))
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wMemW.write('{}\n'.format(storeReg[2:]))
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wMemW.write('{:x}\n'.format(storeLocOffset))
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if readOffset != '' and readLoc != '':
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wMem.write('{:x}\n'.format(int(readOffset,10) + int(readLoc, 16)))
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lastReadLoc = int(readOffset,10) + int(readLoc, 16)
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lastReadType = readType
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readOffset = ''
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readLoc = ''
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curRegs = ''
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instrStart = -1
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lastRead = currentRead
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currentRead = ''
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lastStoreReg = storeReg
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lastStoreLoc = storeLoc
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storeReg = ''
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storeOffset = ''
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storeLoc = ''
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lastAMO = storeAMO
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if curRegs != lastRegs:
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if lastRegs == '':
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wReg.write(curRegs)
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else:
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for i in range(32):
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if curRegs.split('\n')[i] != lastRegs.split('\n')[i]:
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wReg.write('{}\n'.format(i+1))
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wReg.write('{}\n'.format(curRegs.split('\n')[i]))
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break
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lastRegs = curRegs
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if lastAMO != '':
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if 'amoadd' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16) + readData)[2:]
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elif 'amoand' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16) & readData)[2:]
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elif 'amoor' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16) | readData)[2:]
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elif 'amoswap' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16))[2:]
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else:
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print(lastAMO)
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exit()
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#print('lastStoreReg {}\n'.format(lastStoreReg))
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#print('lastStoreLoc '+str(lastStoreLoc))
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wMemW.write('{}\n'.format(lastStoreReg))
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wMemW.write('{:x}\n'.format(int(lastStoreLoc, 16)))
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if storeReg != '' and storeOffset != '' and storeLoc != '' and storeAMO == '':
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storeLocOffset = int(storeOffset,10) + int(storeLoc, 16)
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#wMemW.write('{:x}\n'.format(int(storeReg, 16) << (8 * (storeLocOffset % 8))))
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wMemW.write('{}\n'.format(storeReg[2:]))
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wMemW.write('{:x}\n'.format(storeLocOffset))
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if readOffset != '' and readLoc != '':
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wMem.write('{:x}\n'.format(int(readOffset,10) + int(readLoc, 16)))
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lastReadLoc = int(readOffset,10) + int(readLoc, 16)
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lastReadType = readType
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readOffset = ''
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readLoc = ''
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curRegs = ''
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lineOffset = -1
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lastRead = currentRead
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currentRead = ''
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lastStoreReg = storeReg
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lastStoreLoc = storeLoc
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storeReg = ''
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storeOffset = ''
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storeLoc = ''
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lastAMO = storeAMO
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except (FileNotFoundError):
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@ -39,12 +39,14 @@ def parseCSRs(l):
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csr = l.split()[0]
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val = int(l.split()[1],16)
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if inPageFault:
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if l.startswith("mstatus") or l.startswith("mepc") or l.startswith("mcause") or l.startswith("mtval") or l.startswith("sepc") or l.startswith("scause") or l.startswith("stval"):
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# We do update some CSRs
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CSRs[csr] = val
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else:
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# Others we preserve until changed later
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pageFaultCSRs[csr] = val
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# Not sure if these CSRs should be updated or not during page fault.
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#if l.startswith("mstatus") or l.startswith("mepc") or l.startswith("mcause") or l.startswith("mtval") or l.startswith("sepc") or l.startswith("scause") or l.startswith("stval"):
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# # We do update some CSRs
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# CSRs[csr] = val
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#else:
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# # Others we preserve until changed later
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# pageFaultCSRs[csr] = val
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pageFaultCSRs[csr] = val
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elif pageFaultCSRs and (csr in pageFaultCSRs):
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if (val != pageFaultCSRs[csr]):
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del pageFaultCSRs[csr]
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