forked from Github_Repos/cvw
Working through a combo loop.
This commit is contained in:
Ross Thompson
parent
d6c19e73f4
commit
b4a788c341
@ -7,37 +7,37 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/DataStall
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/DataStall
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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@ -209,35 +209,38 @@ add wave -noupdate -group icache -expand -group memory -group {tag write} /testb
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add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
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add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
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add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/BusState
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/ProposedNextBusState
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/NextBusState
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/DSquashBusAccessM
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/ISquashBusAccessF
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add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
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add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemReadM
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add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemWriteM
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add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HCLK
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HRESETn
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HRDATA
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HREADY
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HRESP
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HADDR
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWDATA
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWRITE
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HSIZE
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HBURST
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HPROT
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HTRANS
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HMASTLOCK
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HADDRD
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/BusState
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/ProposedNextBusState
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/DSquashBusAccessM
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/ISquashBusAccessF
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemReadM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemWriteM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HREADY
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESP
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDR
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWDATA
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITE
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZE
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HBURST
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HPROT
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HTRANS
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -expand -group lsu /testbench/dut/hart/arbiter/MemAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemPAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/AtomicMaskedM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DSquashBusAccessM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAckW
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
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@ -280,7 +283,7 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {14425 ns} 0}
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WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {10763646 ns} 0}
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quietly wave cursor active 2
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 189
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@ -296,4 +299,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {0 ns} {2330991 ns}
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WaveRestoreZoom {10763302 ns} {10763880 ns}
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@ -100,13 +100,14 @@ module lsu (
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logic SquashSCM;
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logic DTLBPageFaultM;
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logic MemAccessM;
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logic [1:0] CurrState, NextState;
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logic [2:0] CurrState, NextState;
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logic preCommittedM;
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localparam STATE_READY = 0;
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localparam STATE_FETCH = 1;
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localparam STATE_FETCH_AMO = 2;
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localparam STATE_STALLED = 3;
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localparam STATE_FETCH_AMO_1 = 2;
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localparam STATE_FETCH_AMO_2 = 3;
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localparam STATE_STALLED = 4;
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logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem
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// *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
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@ -195,31 +196,70 @@ module lsu (
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endgenerate
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// Data stall
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assign DataStall = (NextState == STATE_FETCH) || (NextState == STATE_FETCH_AMO);
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//assign DataStall = (NextState == STATE_FETCH) || (NextState == STATE_FETCH_AMO_1) || (NextState == STATE_FETCH_AMO_2);
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// Ross Thompson April 22, 2021
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// for now we need to handle the issue where the data memory interface repeately
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// requests data from memory rather than issuing a single request.
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flopr #(2) stateReg(.clk(clk),
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flopr #(3) stateReg(.clk(clk),
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.reset(reset),
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.d(NextState),
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.q(CurrState));
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always_comb begin
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case (CurrState)
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STATE_READY: if (|AtomicMaskedM) NextState = STATE_FETCH_AMO; // *** should be some misalign check
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else if (MemAccessM & ~DataMisalignedM) NextState = STATE_FETCH;
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else NextState = STATE_READY;
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STATE_FETCH_AMO: if (MemAckW) NextState = STATE_FETCH;
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else NextState = STATE_FETCH_AMO;
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STATE_FETCH: if (MemAckW & ~StallW) NextState = STATE_READY; // StallW will stay high if datastall stays high, so right now, once we get into STATE_FETCH, datastall goes high, and we never leave
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else if (MemAckW & StallW) NextState = STATE_STALLED;
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else NextState = STATE_FETCH;
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STATE_STALLED: if (~StallW) NextState = STATE_READY;
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else NextState = STATE_STALLED;
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default: NextState = STATE_READY;
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STATE_READY:
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if (|AtomicMaskedM) begin
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NextState = STATE_FETCH_AMO_1; // *** should be some misalign check
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DataStall = 1'b1;
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end else if (MemAccessM & ~DataMisalignedM) begin
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NextState = STATE_FETCH;
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DataStall = 1'b1;
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end else begin
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NextState = STATE_READY;
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DataStall = 1'b0;
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end
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STATE_FETCH_AMO_1:
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DataStall = 1'b1;
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if (MemAckW) begin
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NextState = STATE_FETCH_AMO_2;
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end else begin
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NextState = STATE_FETCH_AMO_1;
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end
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STATE_FETCH_AMO_2: begin
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DataStall = 1'b1;
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if (MemAckW & ~StallW) begin
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NextState = STATE_FETCH_AMO_2;
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end else if (MemAckW & StallW) begin
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NextState = STATE_STALLED;
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end else begin
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NextState = STATE_FETCH_AMO_2;
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end
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end
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STATE_FETCH: begin
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DataStall = 1'b1;
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if (MemAckW & ~StallW) begin
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NextState = STATE_READY;
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end else if (MemAckW & StallW) begin
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NextState = STATE_STALLED;
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end else begin
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NextState = STATE_FETCH;
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end
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end
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STATE_STALLED: begin
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DataStall = 1'b0;
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if (~StallW) begin
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NextState = STATE_READY;
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end else begin
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NextState = STATE_STALLED;
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end
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end
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default: begin
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DataStall = 1'b0;
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NextState = STATE_READY;
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end
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endcase
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end
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