cvw/wally-pipelined
2021-02-26 20:12:27 -06:00
..
bin Updating the test bench to include a function radix. Not done. 2021-02-26 19:43:40 -06:00
config Parallel FSR's and F CTRL logic 2021-02-04 02:25:55 -06:00
regression Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
src Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
testbench Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
testgen added branch tests 2021-02-12 22:40:08 -05:00
lint-wally Reorganized src hierarchically 2021-01-30 11:50:37 -05:00