Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add support for vectored interrupts

Browse Source
This commit is contained in:
Domenico Ottolia 2021-04-15 19:13:42 -04:00
parent eb9e1843fc
commit 92bb38fa8c
5 changed files with 18 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
wally-pipelined/config/busybear/wally-config.vh
View File

@ -56,6 +56,7 @@
`define MEM_DTIM 1
`define MEM_ICACHE 0
`define MEM_VIRTMEM 0
`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
// Address space
`define RESET_VECTOR 64'h0000000000001000

1
wally-pipelined/config/rv32ic/wally-config.vh
View File

@ -54,6 +54,7 @@
`define MEM_DTIM 1
`define MEM_ICACHE 0
`define MEM_VIRTMEM 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
// Address space
`define RESET_VECTOR 32'h80000000

1
wally-pipelined/config/rv64ic/wally-config.vh
View File

@ -55,6 +55,7 @@
`define MEM_DTIM 1
`define MEM_ICACHE 0
`define MEM_VIRTMEM 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
// Address space
`define RESET_VECTOR 64'h0000000080000000

1
wally-pipelined/config/rv64icfd/wally-config.vh
View File

@ -55,6 +55,7 @@
`define MEM_DTIM 1
`define MEM_ICACHE 0
`define MEM_VIRTMEM 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
// Address space
`define RESET_VECTOR 64'h0000000080000000

18
wally-pipelined/src/privileged/trap.sv
View File

@ -2,7 +2,7 @@
// trap.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
// Modified: dottolia@hmc.edu 14 April 2021: Add support for vectored interrupts
//
// Purpose: Handle Traps: Exceptions and Interrupt
// See RISC-V Privileged Mode Specification 20190608 3.1.10-11
@ -47,6 +47,7 @@ module trap (
logic [11:0] MIntGlobalEnM, SIntGlobalEnM, PendingIntsM;
logic InterruptM;
logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
// Determine pending enabled interrupts
assign MIntGlobalEnM = {12{(PrivilegeModeW != `M_MODE) || STATUS_MIE}}; // if M ints enabled or lower priv 3.1.9
@ -64,13 +65,22 @@ module trap (
assign UTrapM = TrapM & (NextPrivilegeModeM == `U_MODE) & `N_SUPPORTED;
assign RetM = mretM | sretM | uretM;
always_comb
if (NextPrivilegeModeM == `U_MODE) PrivilegedTrapVector = UTVEC_REGW;
else if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW;
else PrivilegedTrapVector = MTVEC_REGW;
// Handle vectored traps (when mtvec/stvec/utvec csr value has bits [1:0] == 01)
// For vectored traps, set program counter to _tvec value + 4 times the cause code
assign PrivilegedVectoredTrapVector = PrivilegedTrapVector + {CauseM[`XLEN-3:0], 2'b00};
always_comb
if (mretM) PrivilegedNextPCM = MEPC_REGW;
else if (sretM) PrivilegedNextPCM = SEPC_REGW;
else if (uretM) PrivilegedNextPCM = UEPC_REGW;
else if (NextPrivilegeModeM == `U_MODE) PrivilegedNextPCM = UTVEC_REGW;
else if (NextPrivilegeModeM == `S_MODE) PrivilegedNextPCM = STVEC_REGW;
else PrivilegedNextPCM = MTVEC_REGW;
else if (PrivilegedTrapVector[1:0] == 2'b01 && CauseM[`XLEN-1] == 1)
PrivilegedNextPCM = PrivilegedVectoredTrapVector;
else PrivilegedNextPCM = PrivilegedTrapVector;
// Cause priority defined in table 3.7 of 20190608 privileged spec
// Exceptions are of lower priority than all interrupts (3.1.9)