Ross Thompson f3093ac612 Why was the linter messed up? ... There are a number of combo loops which need fixing outside the icache. They may be fixed in main. We get to instruction address 50 now!		2021-04-20 22:06:12 -05:00
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bin	Added possibly working OSU test bench as a precursor to running a bp benchmark.	2021-03-17 11:06:32 -05:00
config	buildroot: sim is now running!	2021-04-17 14:44:32 -04:00
misc/tlb_toy	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Why was the linter messed up?	2021-04-20 22:06:12 -05:00
src	Why was the linter messed up?	2021-04-20 22:06:12 -05:00
testbench	Broken icache. Design is done. Time to debug.	2021-04-20 19:55:49 -05:00
testgen	Add tests for scause and ucause	2021-04-15 19:41:25 -04:00
lint-wally	Why was the linter messed up?	2021-04-20 22:06:12 -05:00