forked from Github_Repos/cvw
Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported
This commit is contained in:
David Harris
parent
004cac91e1
commit
ac163e091c
@ -43,90 +43,94 @@ module fpu (
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output logic [4:0] SetFflagsM, // FPU flags
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output logic [`XLEN-1:0] FPUResultW); // FPU result
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// *** change FMA to do 16 - 32 - 64 - 128 FEXPBITS
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// control logic signal instantiation
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logic FWriteEnD, FWriteEnE, FWriteEnM, FWriteEnW; // FP register write enable
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logic [2:0] FrmD, FrmE, FrmM; // FP rounding mode
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logic FmtD, FmtE, FmtM, FmtW; // FP precision 0-single 1-double
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logic FDivStartD, FDivStartE; // Start division
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logic FWriteIntD; // Write to integer register
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logic [1:0] ForwardXE, ForwardYE, ForwardZE; // Input3 forwarding mux control signal
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logic [2:0] FResultSelD, FResultSelE, FResultSelM, FResultSelW; // Select FP result
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logic [3:0] FOpCtrlD, FOpCtrlE, FOpCtrlM; // Select which opperation to do in each component
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logic [1:0] FResSelD, FResSelE, FResSelM;
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logic [1:0] FIntResSelD, FIntResSelE, FIntResSelM;
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logic [4:0] Adr1E, Adr2E, Adr3E;
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// regfile signals
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logic [4:0] RdE, RdM, RdW; // what adress to write to // ***Can take from ieu insted of pipelining
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logic [63:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
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logic [63:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
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logic [`XLEN-1:0] SrcXMAligned;
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logic [63:0] SrcXE, SrcXM; // Input 1 to the various units (after forwarding)
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logic [63:0] SrcYE, SrcYM; // Input 2 to the various units (after forwarding)
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logic [63:0] SrcZE, SrcZM; // Input 3 to the various units (after forwarding)
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// div/sqrt signals
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logic [63:0] FDivResultM, FDivResultW;
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logic [4:0] FDivSqrtFlgM, FDivSqrtFlgW;
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logic FDivSqrtDoneE;
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logic [63:0] DivInput1E, DivInput2E;
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logic HoldInputs; // keep forwarded inputs arround durring division
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// FMA signals
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logic [105:0] ProdManE, ProdManM; ///*** put pipline stages in units
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logic [161:0] AlignedAddendE, AlignedAddendM;
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logic [12:0] ProdExpE, ProdExpM;
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logic AddendStickyE, AddendStickyM;
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logic KillProdE, KillProdM;
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logic XZeroE, YZeroE, ZZeroE, XZeroM, YZeroM, ZZeroM;
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logic XInfE, YInfE, ZInfE, XInfM, YInfM, ZInfM;
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logic XNaNE, YNaNE, ZNaNE, XNaNM, YNaNM, ZNaNM;
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logic [63:0] FMAResM, FMAResW;
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logic [4:0] FMAFlgM, FMAFlgW;
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// add/cvt signals
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logic [63:0] AddSumE, AddSumM;
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logic [63:0] AddSumTcE, AddSumTcM;
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logic [3:0] AddSelInvE, AddSelInvM;
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logic [10:0] AddExpPostSumE,AddExpPostSumM;
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logic AddCorrSignE, AddCorrSignM;
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logic AddOp1NormE, AddOp1NormM;
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logic AddOp2NormE, AddOp2NormM;
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logic AddOpANormE, AddOpANormM;
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logic AddOpBNormE, AddOpBNormM;
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logic AddInvalidE, AddInvalidM;
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logic AddDenormInE, AddDenormInM;
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logic AddSwapE, AddSwapM;
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logic AddNormOvflowE, AddNormOvflowM; //***this isn't used in addcvt2
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logic AddSignAE, AddSignAM;
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logic AddConvertE, AddConvertM;
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logic [63:0] AddFloat1E, AddFloat2E, AddFloat1M, AddFloat2M;
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logic [11:0] AddExp1DenormE, AddExp2DenormE, AddExp1DenormM, AddExp2DenormM;
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logic [10:0] AddExponentE, AddExponentM;
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logic [63:0] FAddResM, FAddResW;
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logic [4:0] FAddFlgM, FAddFlgW;
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// cmp signals
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logic CmpNVE, CmpNVM, CmpNVW;
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logic [63:0] CmpResE, CmpResM, CmpResW;
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// fsgn signals
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logic [63:0] SgnResE, SgnResM;
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logic SgnNVE, SgnNVM, SgnNVW;
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logic [63:0] FResM, FResW;
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logic FFlgM, FFlgW;
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// instantiation of W stage regfile signals
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logic [63:0] AlignedSrcAM;
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// classify signals
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logic [63:0] ClassResE, ClassResM;
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// 64-bit FPU result
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logic [63:0] FPUResult64W;
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logic [4:0] FPUFlagsW;
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/*generate
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if (`F_SUPPORTED) begin */
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// control logic signal instantiation
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logic FWriteEnD, FWriteEnE, FWriteEnM, FWriteEnW; // FP register write enable
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logic [2:0] FrmD, FrmE, FrmM; // FP rounding mode
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logic FmtD, FmtE, FmtM, FmtW; // FP precision 0-single 1-double
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logic FDivStartD, FDivStartE; // Start division
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logic FWriteIntD; // Write to integer register
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logic [1:0] ForwardXE, ForwardYE, ForwardZE; // Input3 forwarding mux control signal
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logic [2:0] FResultSelD, FResultSelE, FResultSelM, FResultSelW; // Select FP result
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logic [3:0] FOpCtrlD, FOpCtrlE, FOpCtrlM; // Select which opperation to do in each component
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logic [1:0] FResSelD, FResSelE, FResSelM;
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logic [1:0] FIntResSelD, FIntResSelE, FIntResSelM;
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logic [4:0] Adr1E, Adr2E, Adr3E;
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// regfile signals
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logic [4:0] RdE, RdM, RdW; // what adress to write to // ***Can take from ieu insted of pipelining
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logic [63:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
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logic [63:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
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logic [`XLEN-1:0] SrcXMAligned;
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logic [63:0] SrcXE, SrcXM; // Input 1 to the various units (after forwarding)
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logic [63:0] SrcYE, SrcYM; // Input 2 to the various units (after forwarding)
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logic [63:0] SrcZE, SrcZM; // Input 3 to the various units (after forwarding)
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// div/sqrt signals
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logic [63:0] FDivResultM, FDivResultW;
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logic [4:0] FDivSqrtFlgM, FDivSqrtFlgW;
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logic FDivSqrtDoneE;
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logic [63:0] DivInput1E, DivInput2E;
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logic HoldInputs; // keep forwarded inputs arround durring division
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// FMA signals
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logic [105:0] ProdManE, ProdManM; ///*** put pipline stages in units
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logic [161:0] AlignedAddendE, AlignedAddendM;
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logic [12:0] ProdExpE, ProdExpM;
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logic AddendStickyE, AddendStickyM;
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logic KillProdE, KillProdM;
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logic XZeroE, YZeroE, ZZeroE, XZeroM, YZeroM, ZZeroM;
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logic XInfE, YInfE, ZInfE, XInfM, YInfM, ZInfM;
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logic XNaNE, YNaNE, ZNaNE, XNaNM, YNaNM, ZNaNM;
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logic [63:0] FMAResM, FMAResW;
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logic [4:0] FMAFlgM, FMAFlgW;
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// add/cvt signals
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logic [63:0] AddSumE, AddSumM;
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logic [63:0] AddSumTcE, AddSumTcM;
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logic [3:0] AddSelInvE, AddSelInvM;
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logic [10:0] AddExpPostSumE,AddExpPostSumM;
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logic AddCorrSignE, AddCorrSignM;
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logic AddOp1NormE, AddOp1NormM;
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logic AddOp2NormE, AddOp2NormM;
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logic AddOpANormE, AddOpANormM;
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logic AddOpBNormE, AddOpBNormM;
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logic AddInvalidE, AddInvalidM;
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logic AddDenormInE, AddDenormInM;
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logic AddSwapE, AddSwapM;
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logic AddNormOvflowE, AddNormOvflowM; //***this isn't used in addcvt2
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logic AddSignAE, AddSignAM;
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logic AddConvertE, AddConvertM;
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logic [63:0] AddFloat1E, AddFloat2E, AddFloat1M, AddFloat2M;
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logic [11:0] AddExp1DenormE, AddExp2DenormE, AddExp1DenormM, AddExp2DenormM;
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logic [10:0] AddExponentE, AddExponentM;
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logic [63:0] FAddResM, FAddResW;
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logic [4:0] FAddFlgM, FAddFlgW;
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// cmp signals
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logic CmpNVE, CmpNVM, CmpNVW;
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logic [63:0] CmpResE, CmpResM, CmpResW;
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// fsgn signals
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logic [63:0] SgnResE, SgnResM;
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logic SgnNVE, SgnNVM, SgnNVW;
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logic [63:0] FResM, FResW;
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logic FFlgM, FFlgW;
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// instantiation of W stage regfile signals
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logic [63:0] AlignedSrcAM;
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// classify signals
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logic [63:0] ClassResE, ClassResM;
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// 64-bit FPU result
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logic [63:0] FPUResult64W;
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logic [4:0] FPUFlagsW;
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@ -134,189 +138,19 @@ module fpu (
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//DECODE STAGE
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// top-level controller for FPU
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fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]),
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.FRM_REGW, .IllegalFPUInstrD, .FWriteEnD, .FDivStartD, .FResultSelD, .FOpCtrlD, .FResSelD,
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.FIntResSelD, .FmtD, .FrmD, .FWriteIntD);
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// regfile instantiation
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fregfile fregfile (clk, reset, FWriteEnW,
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InstrD[19:15], InstrD[24:20], InstrD[31:27], RdW,
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FPUResult64W,
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FRD1D, FRD2D, FRD3D);
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//*****************
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// D/E pipe registers
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//*****************
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flopenrc #(64) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
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flopenrc #(64) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
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flopenrc #(64) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
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flopenrc #(1) DECtrlRegE1(clk, reset, FlushE, ~StallE, FDivStartD, FDivStartE);
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flopenrc #(15) DECtrlRegE2(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]},
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{Adr1E, Adr2E, Adr3E});
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flopenrc #(22) DECtrlReg3(clk, reset, FlushE, ~StallE,
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{FWriteEnD, FResultSelD, FResSelD, FIntResSelD, FrmD, FmtD, InstrD[11:7], FOpCtrlD, FWriteIntD},
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{FWriteEnE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, RdE, FOpCtrlE, FWriteIntE});
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//EXECUTION STAGE
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// Hazard unit for FPU
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fhazard fhazard(.Adr1E, .Adr2E, .Adr3E, .FWriteEnM, .FWriteEnW, .RdM, .RdW, .FResultSelM, .FStallD,
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.ForwardXE, .ForwardYE, .ForwardZE);
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// forwarding muxs
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mux3 #(64) fxemux(FRD1E, FPUResult64W, FResM, ForwardXE, SrcXE);
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mux3 #(64) fyemux(FRD2E, FPUResult64W, FResM, ForwardYE, SrcYE);
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mux3 #(64) fzemux(FRD3E, FPUResult64W, FResM, ForwardZE, SrcZE);
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// first of two-stage instance of floating-point fused multiply-add unit
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fma1 fma1 (.X(SrcXE), .Y(SrcYE), .Z(SrcZE), .FOpCtrlE(FOpCtrlE[2:0]), .FmtE, .ProdManE, .AlignedAddendE,
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.ProdExpE, .AddendStickyE, .KillProdE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE,
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.XNaNE, .YNaNE, .ZNaNE );
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// first and only instance of floating-point divider
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logic fpdivClk;
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clockgater fpdivclkg(.E(FDivStartE),
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.SE(1'b0),
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.CLK(clk),
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.ECLK(fpdivClk));
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// capture the inputs for div/sqrt
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flopenrc #(64) reg_input1 (.d(SrcXE), .q(DivInput1E),
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.en(~HoldInputs), .clear(FDivSqrtDoneE),
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.reset(reset), .clk(clk));
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flopenrc #(64) reg_input2 (.d(SrcYE), .q(DivInput2E),
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.en(~HoldInputs), .clear(FDivSqrtDoneE),
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.reset(reset), .clk(clk));
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fdivsqrt fdivsqrt (.DivOpType(FOpCtrlE[0]), .clk(fpdivClk), .FmtE(~FmtE), .DivInput1E, .DivInput2E,
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.FrmE, .DivOvEn(1'b1), .DivUnEn(1'b1), .FDivStartE, .FDivResultM, .FDivSqrtFlgM,
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.FDivSqrtDoneE, .FDivBusyE, .HoldInputs, .reset);
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// first of two-stage instance of floating-point add/cvt unit
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fpuaddcvt1 fpadd1 (.SrcXE, .SrcYE, .FOpCtrlE, .FmtE, .AddFloat1E, .AddFloat2E, .AddExponentE,
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.AddExpPostSumE, .AddExp1DenormE, .AddExp2DenormE, .AddSumE, .AddSumTcE, .AddSelInvE,
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.AddCorrSignE, .AddSignAE, .AddOp1NormE, .AddOp2NormE, .AddOpANormE, .AddOpBNormE, .AddInvalidE,
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.AddDenormInE, .AddConvertE, .AddSwapE, .AddNormOvflowE);
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// first and only instance of floating-point comparator
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fcmp fcmp (SrcXE, SrcYE, FOpCtrlE[2:0], FmtE, CmpNVE, CmpResE);
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// first and only instance of floating-point sign converter
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fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .SrcXE, .SrcYE, .SgnResE, .SgnNVE);
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// first and only instance of floating-point classify unit
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fclassify fclassify (.SrcXE, .FmtE, .ClassResE);
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// output for store instructions
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assign FWriteDataE = FmtE ? SrcYE[63:64-`XLEN] : {{`XLEN-32{1'b0}}, SrcYE[63:32]};
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//***swap to mux
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//*****************
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// E/M pipe registers
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//*****************
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flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, SrcXE, SrcXM);
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flopenrc #(64) EMFpReg2(clk, reset, FlushM, ~StallM, SrcYE, SrcYM);
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flopenrc #(64) EMFpReg3(clk, reset, FlushM, ~StallM, SrcZE, SrcZM);
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flopenrc #(106) EMRegFma1(clk, reset, FlushM, ~StallM, ProdManE, ProdManM);
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flopenrc #(162) EMRegFma2(clk, reset, FlushM, ~StallM, AlignedAddendE, AlignedAddendM);
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flopenrc #(13) EMRegFma3(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM);
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flopenrc #(11) EMRegFma4(clk, reset, FlushM, ~StallM,
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{AddendStickyE, KillProdE, XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE},
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{AddendStickyM, KillProdM, XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM});
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flopenrc #(64) EMRegAdd1(clk, reset, FlushM, ~StallM, AddSumE, AddSumM);
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flopenrc #(64) EMRegAdd2(clk, reset, FlushM, ~StallM, AddSumTcE, AddSumTcM);
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flopenrc #(11) EMRegAdd3(clk, reset, FlushM, ~StallM, AddExpPostSumE, AddExpPostSumM);
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flopenrc #(64) EMRegAdd4(clk, reset, FlushM, ~StallM, AddFloat1E, AddFloat1M);
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flopenrc #(64) EMRegAdd5(clk, reset, FlushM, ~StallM, AddFloat2E, AddFloat2M);
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flopenrc #(12) EMRegAdd6(clk, reset, FlushM, ~StallM, AddExp1DenormE, AddExp1DenormM);
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flopenrc #(12) EMRegAdd7(clk, reset, FlushM, ~StallM, AddExp2DenormE, AddExp2DenormM);
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flopenrc #(11) EMRegAdd8(clk, reset, FlushM, ~StallM, AddExponentE, AddExponentM);
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flopenrc #(15) EMRegAdd9(clk, reset, FlushM, ~StallM,
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{AddSelInvE, AddCorrSignE, AddOp1NormE, AddOp2NormE, AddOpANormE, AddOpBNormE, AddInvalidE, AddDenormInE, AddConvertE, AddSwapE, AddNormOvflowE, AddSignAE},
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{AddSelInvM, AddCorrSignM, AddOp1NormM, AddOp2NormM, AddOpANormM, AddOpBNormM, AddInvalidM, AddDenormInM, AddConvertM, AddSwapM, AddNormOvflowM, AddSignAM});
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flopenrc #(1) EMRegCmp1(clk, reset, FlushM, ~StallM, CmpNVE, CmpNVM);
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flopenrc #(64) EMRegCmp2(clk, reset, FlushM, ~StallM, CmpResE, CmpResM);
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flopenrc #(64) EMRegSgn1(clk, reset, FlushM, ~StallM, SgnResE, SgnResM);
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flopenrc #(1) EMRegSgn2(clk, reset, FlushM, ~StallM, SgnNVE, SgnNVM);
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flopenrc #(22) EMCtrlReg(clk, reset, FlushM, ~StallM,
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{FWriteEnE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, RdE, FOpCtrlE, FWriteIntE},
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{FWriteEnM, FResultSelM, FResSelM, FIntResSelM, FrmM, FmtM, RdM, FOpCtrlM, FWriteIntM});
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flopenrc #(64) EMRegClass(clk, reset, FlushM, ~StallM, ClassResE, ClassResM);
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//BEGIN MEMORY STAGE
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mux3 #(64) FResMux(AlignedSrcAM, SgnResM, CmpResM, FResSelM, FResM);
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mux3 #(1) FFlgMux(1'b0, SgnNVM, CmpNVM, FResSelM, FFlgM);
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//***change to mux
|
||||
assign SrcXMAligned = FmtM ? SrcXM[63:64-`XLEN] : {{`XLEN-32{1'b0}}, SrcXM[63:32]};
|
||||
mux3 #(`XLEN) IntResMux(CmpResM[`XLEN-1:0], SrcXMAligned, ClassResM[`XLEN-1:0], FIntResSelM, FIntResM);
|
||||
|
||||
// second instance of two-stage FMA unit
|
||||
fma2 fma2(.X(SrcXM), .Y(SrcYM), .Z(SrcZM), .FOpCtrlM(FOpCtrlM[2:0]), .FrmM, .FmtM,
|
||||
.ProdManM, .AlignedAddendM, .ProdExpM, .AddendStickyM, .KillProdM,
|
||||
.XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM,
|
||||
.FMAResM, .FMAFlgM);
|
||||
|
||||
// second instance of two-stage floating-point add/cvt unit
|
||||
fpuaddcvt2 fpadd2 (.FrmM, .FOpCtrlM, .FmtM, .AddSumM, .AddSumTcM, .AddFloat1M, .AddFloat2M,
|
||||
.AddExp1DenormM, .AddExp2DenormM, .AddExponentM, .AddExpPostSumM, .AddSelInvM,
|
||||
.AddOp1NormM, .AddOp2NormM, .AddOpANormM, .AddOpBNormM, .AddInvalidM, .AddDenormInM,
|
||||
.AddSignAM, .AddCorrSignM, .AddConvertM, .AddSwapM, .FAddResM, .FAddFlgM);
|
||||
|
||||
// Align SrcA to MSB when single precicion
|
||||
mux2 #(64) SrcAMux({SrcAM[31:0], 32'b0}, {{64-`XLEN{1'b0}}, SrcAM}, FmtM, AlignedSrcAM);
|
||||
//DECODE STAGE
|
||||
|
||||
|
||||
// top-level controller for FPU
|
||||
fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]),
|
||||
.FRM_REGW, .IllegalFPUInstrD, .FWriteEnD, .FDivStartD, .FResultSelD, .FOpCtrlD, .FResSelD,
|
||||
.FIntResSelD, .FmtD, .FrmD, .FWriteIntD);
|
||||
|
||||
// regfile instantiation
|
||||
fregfile fregfile (clk, reset, FWriteEnW,
|
||||
InstrD[19:15], InstrD[24:20], InstrD[31:27], RdW,
|
||||
FPUResult64W,
|
||||
FRD1D, FRD2D, FRD3D);
|
||||
|
||||
|
||||
|
||||
@ -326,77 +160,261 @@ module fpu (
|
||||
|
||||
|
||||
|
||||
//*****************
|
||||
// D/E pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
|
||||
flopenrc #(64) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
|
||||
flopenrc #(64) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
|
||||
flopenrc #(1) DECtrlRegE1(clk, reset, FlushE, ~StallE, FDivStartD, FDivStartE);
|
||||
flopenrc #(15) DECtrlRegE2(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]},
|
||||
{Adr1E, Adr2E, Adr3E});
|
||||
flopenrc #(22) DECtrlReg3(clk, reset, FlushE, ~StallE,
|
||||
{FWriteEnD, FResultSelD, FResSelD, FIntResSelD, FrmD, FmtD, InstrD[11:7], FOpCtrlD, FWriteIntD},
|
||||
{FWriteEnE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, RdE, FOpCtrlE, FWriteIntE});
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//EXECUTION STAGE
|
||||
|
||||
// Hazard unit for FPU
|
||||
fhazard fhazard(.Adr1E, .Adr2E, .Adr3E, .FWriteEnM, .FWriteEnW, .RdM, .RdW, .FResultSelM, .FStallD,
|
||||
.ForwardXE, .ForwardYE, .ForwardZE);
|
||||
|
||||
// forwarding muxs
|
||||
mux3 #(64) fxemux(FRD1E, FPUResult64W, FResM, ForwardXE, SrcXE);
|
||||
mux3 #(64) fyemux(FRD2E, FPUResult64W, FResM, ForwardYE, SrcYE);
|
||||
mux3 #(64) fzemux(FRD3E, FPUResult64W, FResM, ForwardZE, SrcZE);
|
||||
|
||||
|
||||
// first of two-stage instance of floating-point fused multiply-add unit
|
||||
fma1 fma1 (.X(SrcXE), .Y(SrcYE), .Z(SrcZE), .FOpCtrlE(FOpCtrlE[2:0]), .FmtE, .ProdManE, .AlignedAddendE,
|
||||
.ProdExpE, .AddendStickyE, .KillProdE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE,
|
||||
.XNaNE, .YNaNE, .ZNaNE );
|
||||
|
||||
// first and only instance of floating-point divider
|
||||
logic fpdivClk;
|
||||
|
||||
clockgater fpdivclkg(.E(FDivStartE),
|
||||
.SE(1'b0),
|
||||
.CLK(clk),
|
||||
.ECLK(fpdivClk));
|
||||
|
||||
// capture the inputs for div/sqrt
|
||||
flopenrc #(64) reg_input1 (.d(SrcXE), .q(DivInput1E),
|
||||
.en(~HoldInputs), .clear(FDivSqrtDoneE),
|
||||
.reset(reset), .clk(clk));
|
||||
flopenrc #(64) reg_input2 (.d(SrcYE), .q(DivInput2E),
|
||||
.en(~HoldInputs), .clear(FDivSqrtDoneE),
|
||||
.reset(reset), .clk(clk));
|
||||
|
||||
fdivsqrt fdivsqrt (.DivOpType(FOpCtrlE[0]), .clk(fpdivClk), .FmtE(~FmtE), .DivInput1E, .DivInput2E,
|
||||
.FrmE, .DivOvEn(1'b1), .DivUnEn(1'b1), .FDivStartE, .FDivResultM, .FDivSqrtFlgM,
|
||||
.FDivSqrtDoneE, .FDivBusyE, .HoldInputs, .reset);
|
||||
|
||||
|
||||
|
||||
// first of two-stage instance of floating-point add/cvt unit
|
||||
fpuaddcvt1 fpadd1 (.SrcXE, .SrcYE, .FOpCtrlE, .FmtE, .AddFloat1E, .AddFloat2E, .AddExponentE,
|
||||
.AddExpPostSumE, .AddExp1DenormE, .AddExp2DenormE, .AddSumE, .AddSumTcE, .AddSelInvE,
|
||||
.AddCorrSignE, .AddSignAE, .AddOp1NormE, .AddOp2NormE, .AddOpANormE, .AddOpBNormE, .AddInvalidE,
|
||||
.AddDenormInE, .AddConvertE, .AddSwapE, .AddNormOvflowE);
|
||||
|
||||
// first and only instance of floating-point comparator
|
||||
fcmp fcmp (SrcXE, SrcYE, FOpCtrlE[2:0], FmtE, CmpNVE, CmpResE);
|
||||
|
||||
// first and only instance of floating-point sign converter
|
||||
fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .SrcXE, .SrcYE, .SgnResE, .SgnNVE);
|
||||
|
||||
// first and only instance of floating-point classify unit
|
||||
fclassify fclassify (.SrcXE, .FmtE, .ClassResE);
|
||||
|
||||
// output for store instructions
|
||||
assign FWriteDataE = FmtE ? SrcYE[63:64-`XLEN] : {{`XLEN-32{1'b0}}, SrcYE[63:32]};
|
||||
//***swap to mux
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//*****************
|
||||
// E/M pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, SrcXE, SrcXM);
|
||||
flopenrc #(64) EMFpReg2(clk, reset, FlushM, ~StallM, SrcYE, SrcYM);
|
||||
flopenrc #(64) EMFpReg3(clk, reset, FlushM, ~StallM, SrcZE, SrcZM);
|
||||
|
||||
flopenrc #(106) EMRegFma1(clk, reset, FlushM, ~StallM, ProdManE, ProdManM);
|
||||
flopenrc #(162) EMRegFma2(clk, reset, FlushM, ~StallM, AlignedAddendE, AlignedAddendM);
|
||||
flopenrc #(13) EMRegFma3(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM);
|
||||
flopenrc #(11) EMRegFma4(clk, reset, FlushM, ~StallM,
|
||||
{AddendStickyE, KillProdE, XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE},
|
||||
{AddendStickyM, KillProdM, XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM});
|
||||
|
||||
flopenrc #(64) EMRegAdd1(clk, reset, FlushM, ~StallM, AddSumE, AddSumM);
|
||||
flopenrc #(64) EMRegAdd2(clk, reset, FlushM, ~StallM, AddSumTcE, AddSumTcM);
|
||||
flopenrc #(11) EMRegAdd3(clk, reset, FlushM, ~StallM, AddExpPostSumE, AddExpPostSumM);
|
||||
flopenrc #(64) EMRegAdd4(clk, reset, FlushM, ~StallM, AddFloat1E, AddFloat1M);
|
||||
flopenrc #(64) EMRegAdd5(clk, reset, FlushM, ~StallM, AddFloat2E, AddFloat2M);
|
||||
flopenrc #(12) EMRegAdd6(clk, reset, FlushM, ~StallM, AddExp1DenormE, AddExp1DenormM);
|
||||
flopenrc #(12) EMRegAdd7(clk, reset, FlushM, ~StallM, AddExp2DenormE, AddExp2DenormM);
|
||||
flopenrc #(11) EMRegAdd8(clk, reset, FlushM, ~StallM, AddExponentE, AddExponentM);
|
||||
flopenrc #(15) EMRegAdd9(clk, reset, FlushM, ~StallM,
|
||||
{AddSelInvE, AddCorrSignE, AddOp1NormE, AddOp2NormE, AddOpANormE, AddOpBNormE, AddInvalidE, AddDenormInE, AddConvertE, AddSwapE, AddNormOvflowE, AddSignAE},
|
||||
{AddSelInvM, AddCorrSignM, AddOp1NormM, AddOp2NormM, AddOpANormM, AddOpBNormM, AddInvalidM, AddDenormInM, AddConvertM, AddSwapM, AddNormOvflowM, AddSignAM});
|
||||
|
||||
flopenrc #(1) EMRegCmp1(clk, reset, FlushM, ~StallM, CmpNVE, CmpNVM);
|
||||
flopenrc #(64) EMRegCmp2(clk, reset, FlushM, ~StallM, CmpResE, CmpResM);
|
||||
|
||||
flopenrc #(64) EMRegSgn1(clk, reset, FlushM, ~StallM, SgnResE, SgnResM);
|
||||
flopenrc #(1) EMRegSgn2(clk, reset, FlushM, ~StallM, SgnNVE, SgnNVM);
|
||||
|
||||
flopenrc #(22) EMCtrlReg(clk, reset, FlushM, ~StallM,
|
||||
{FWriteEnE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, RdE, FOpCtrlE, FWriteIntE},
|
||||
{FWriteEnM, FResultSelM, FResSelM, FIntResSelM, FrmM, FmtM, RdM, FOpCtrlM, FWriteIntM});
|
||||
|
||||
flopenrc #(64) EMRegClass(clk, reset, FlushM, ~StallM, ClassResE, ClassResM);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//BEGIN MEMORY STAGE
|
||||
|
||||
mux3 #(64) FResMux(AlignedSrcAM, SgnResM, CmpResM, FResSelM, FResM);
|
||||
mux3 #(1) FFlgMux(1'b0, SgnNVM, CmpNVM, FResSelM, FFlgM);
|
||||
|
||||
//***change to mux
|
||||
assign SrcXMAligned = FmtM ? SrcXM[63:64-`XLEN] : {{`XLEN-32{1'b0}}, SrcXM[63:32]};
|
||||
mux3 #(`XLEN) IntResMux(CmpResM[`XLEN-1:0], SrcXMAligned, ClassResM[`XLEN-1:0], FIntResSelM, FIntResM);
|
||||
|
||||
// second instance of two-stage FMA unit
|
||||
fma2 fma2(.X(SrcXM), .Y(SrcYM), .Z(SrcZM), .FOpCtrlM(FOpCtrlM[2:0]), .FrmM, .FmtM,
|
||||
.ProdManM, .AlignedAddendM, .ProdExpM, .AddendStickyM, .KillProdM,
|
||||
.XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM,
|
||||
.FMAResM, .FMAFlgM);
|
||||
|
||||
// second instance of two-stage floating-point add/cvt unit
|
||||
fpuaddcvt2 fpadd2 (.FrmM, .FOpCtrlM, .FmtM, .AddSumM, .AddSumTcM, .AddFloat1M, .AddFloat2M,
|
||||
.AddExp1DenormM, .AddExp2DenormM, .AddExponentM, .AddExpPostSumM, .AddSelInvM,
|
||||
.AddOp1NormM, .AddOp2NormM, .AddOpANormM, .AddOpBNormM, .AddInvalidM, .AddDenormInM,
|
||||
.AddSignAM, .AddCorrSignM, .AddConvertM, .AddSwapM, .FAddResM, .FAddFlgM);
|
||||
|
||||
// Align SrcA to MSB when single precicion
|
||||
mux2 #(64) SrcAMux({SrcAM[31:0], 32'b0}, {{64-`XLEN{1'b0}}, SrcAM}, FmtM, AlignedSrcAM);
|
||||
|
||||
//*****************
|
||||
// M/W pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) MWRegFma1(clk, reset, FlushW, ~StallW, FMAResM, FMAResW);
|
||||
flopenrc #(5) MWRegFma2(clk, reset, FlushW, ~StallW, FMAFlgM, FMAFlgW);
|
||||
|
||||
flopenrc #(64) MWRegDiv1(clk, reset, FlushW, ~StallW, FDivResultM, FDivResultW);
|
||||
flopenrc #(5) MWRegDiv2(clk, reset, FlushW, ~StallW, FDivSqrtFlgM, FDivSqrtFlgW);
|
||||
|
||||
flopenrc #(64) MWRegAdd1(clk, reset, FlushW, ~StallW, FAddResM, FAddResW);
|
||||
flopenrc #(5) MWRegAdd2(clk, reset, FlushW, ~StallW, FAddFlgM, FAddFlgW);
|
||||
|
||||
flopenrc #(1) MWRegCmp1(clk, reset, FlushW, ~StallW, CmpNVM, CmpNVW);
|
||||
flopenrc #(64) MWRegCmp3(clk, reset, FlushW, ~StallW, CmpResM, CmpResW);
|
||||
|
||||
flopenrc #(64) MWRegClass2(clk, reset, FlushW, ~StallW, FResM, FResW);
|
||||
flopenrc #(1) MWRegClass1(clk, reset, FlushW, ~StallW, FFlgM, FFlgW);
|
||||
|
||||
flopenrc #(11) MWCtrlReg(clk, reset, FlushW, ~StallW,
|
||||
{FWriteEnM, FResultSelM, RdM, FmtM, FWriteIntM},
|
||||
{FWriteEnW, FResultSelW, RdW, FmtW, FWriteIntW});
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//#########################################
|
||||
// BEGIN WRITEBACK STAGE
|
||||
//#########################################
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//***turn into muxs
|
||||
always_comb begin
|
||||
case (FResultSelW)
|
||||
3'b000 : FPUFlagsW = 5'b0;
|
||||
3'b001 : FPUFlagsW = FMAFlgW;
|
||||
3'b010 : FPUFlagsW = FAddFlgW;
|
||||
3'b011 : FPUFlagsW = FDivSqrtFlgW;
|
||||
3'b100 : FPUFlagsW = {4'b0,FFlgW};
|
||||
default : FPUFlagsW = 5'bxxxxx;
|
||||
endcase
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
case (FResultSelW)
|
||||
3'b000 : FPUResult64W = FmtW ? {ReadDataW, {64-`XLEN{1'b0}}} : {ReadDataW[31:0], 32'b0};
|
||||
3'b001 : FPUResult64W = FMAResW;
|
||||
3'b010 : FPUResult64W = FAddResW;
|
||||
3'b011 : FPUResult64W = FDivResultW;
|
||||
3'b100 : FPUResult64W = FResW;
|
||||
default : FPUResult64W = 64'bxxxxx;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
// interface between XLEN size datapath and double-precision sized
|
||||
// floating-point results
|
||||
//
|
||||
// define offsets for LSB zero extension or truncation
|
||||
always_comb begin
|
||||
// zero extension
|
||||
//***turn into mux
|
||||
FPUResultW = FmtW ? FPUResult64W[63:64-`XLEN] : {{`XLEN-32{1'b0}}, FPUResult64W[63:32]};
|
||||
//*** put into mem stage
|
||||
SetFflagsM = FPUFlagsW;
|
||||
|
||||
|
||||
|
||||
|
||||
//*****************
|
||||
// M/W pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) MWRegFma1(clk, reset, FlushW, ~StallW, FMAResM, FMAResW);
|
||||
flopenrc #(5) MWRegFma2(clk, reset, FlushW, ~StallW, FMAFlgM, FMAFlgW);
|
||||
|
||||
flopenrc #(64) MWRegDiv1(clk, reset, FlushW, ~StallW, FDivResultM, FDivResultW);
|
||||
flopenrc #(5) MWRegDiv2(clk, reset, FlushW, ~StallW, FDivSqrtFlgM, FDivSqrtFlgW);
|
||||
|
||||
flopenrc #(64) MWRegAdd1(clk, reset, FlushW, ~StallW, FAddResM, FAddResW);
|
||||
flopenrc #(5) MWRegAdd2(clk, reset, FlushW, ~StallW, FAddFlgM, FAddFlgW);
|
||||
|
||||
flopenrc #(1) MWRegCmp1(clk, reset, FlushW, ~StallW, CmpNVM, CmpNVW);
|
||||
flopenrc #(64) MWRegCmp3(clk, reset, FlushW, ~StallW, CmpResM, CmpResW);
|
||||
|
||||
flopenrc #(64) MWRegClass2(clk, reset, FlushW, ~StallW, FResM, FResW);
|
||||
flopenrc #(1) MWRegClass1(clk, reset, FlushW, ~StallW, FFlgM, FFlgW);
|
||||
|
||||
flopenrc #(11) MWCtrlReg(clk, reset, FlushW, ~StallW,
|
||||
{FWriteEnM, FResultSelM, RdM, FmtM, FWriteIntM},
|
||||
{FWriteEnW, FResultSelW, RdW, FmtW, FWriteIntW});
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//#########################################
|
||||
// BEGIN WRITEBACK STAGE
|
||||
//#########################################
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//***turn into muxs
|
||||
always_comb begin
|
||||
case (FResultSelW)
|
||||
3'b000 : FPUFlagsW = 5'b0;
|
||||
3'b001 : FPUFlagsW = FMAFlgW;
|
||||
3'b010 : FPUFlagsW = FAddFlgW;
|
||||
3'b011 : FPUFlagsW = FDivSqrtFlgW;
|
||||
3'b100 : FPUFlagsW = {4'b0,FFlgW};
|
||||
default : FPUFlagsW = 5'bxxxxx;
|
||||
endcase
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
case (FResultSelW)
|
||||
3'b000 : FPUResult64W = FmtW ? {ReadDataW, {64-`XLEN{1'b0}}} : {ReadDataW[31:0], 32'b0};
|
||||
3'b001 : FPUResult64W = FMAResW;
|
||||
3'b010 : FPUResult64W = FAddResW;
|
||||
3'b011 : FPUResult64W = FDivResultW;
|
||||
3'b100 : FPUResult64W = FResW;
|
||||
default : FPUResult64W = 64'bxxxxx;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
// interface between XLEN size datapath and double-precision sized
|
||||
// floating-point results
|
||||
//
|
||||
// define offsets for LSB zero extension or truncation
|
||||
always_comb begin
|
||||
// zero extension
|
||||
//***turn into mux
|
||||
FPUResultW = FmtW ? FPUResult64W[63:64-`XLEN] : {{`XLEN-32{1'b0}}, FPUResult64W[63:32]};
|
||||
//*** put into mem stage
|
||||
SetFflagsM = FPUFlagsW;
|
||||
end
|
||||
|
||||
/* end else begin
|
||||
assign FStallD = 0;
|
||||
assign FWriteIntE = 0;
|
||||
assign FWriteIntM = 0;
|
||||
assign FWriteIntW = 0;
|
||||
assign FWriteDataE = 0;
|
||||
assign FIntResM = 0;
|
||||
assign FDivBusyE = 0;
|
||||
assign IllegalFPUInstrD = 0;
|
||||
assign SetFflagsM = 0;
|
||||
assign FPUResultW = 0;
|
||||
end
|
||||
endgenerate*/
|
||||
|
||||
endmodule // fpu
|
||||
|
||||
|
||||
@ -138,7 +138,9 @@ module muldiv (
|
||||
flopenrc #(`XLEN) MulDivResultWReg(clk, reset, FlushW, ~StallW, MulDivResultM, MulDivResultW);
|
||||
|
||||
end else begin // no M instructions supported
|
||||
assign MulDivResultW = 0;
|
||||
assign MulDivResultW = 0;
|
||||
assign DivBusyE = 0;
|
||||
assign DivDoneE = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user