forked from Github_Repos/cvw
		
	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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						commit
						82b4d42f32
					
				@ -1,9 +1,11 @@
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#!/bin/bash
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# check for warnings in Verilog code
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# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
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basepath=$(dirname $0)
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for config in rv64ic rv32ic; do
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    echo "$config linting..."
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    if !(verilator --lint-only "$@" --top-module wallypipelinedsoc "-Iconfig/$config" src/*/*.sv); then
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    if !(verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/$config" $basepath/src/*/*.sv); then
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        echo "Exiting after $config lint due to errors or warnings"
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        exit 1
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    fi
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@ -36,6 +36,11 @@ configs = [
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        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do ../config/rv64ic rv64ic\n!",
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        grepstr="All tests ran without failures"
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    ),
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    Config(
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        name="lints",
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        cmd="../lint-wally > {}",
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        grepstr="All lints run with no errors or warnings"
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    ),
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]
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import multiprocessing, os
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