forked from Github_Repos/cvw
The icache now correctly interlocks with the PTW on TLB miss.
This commit is contained in:
Ross Thompson
parent
dd84f2958e
commit
b2d8ba6742
@ -7,37 +7,37 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/DataStall
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/DataStall
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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@ -130,9 +130,6 @@ add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/MemAdrM
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/WriteDataM
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add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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@ -175,42 +172,43 @@ add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
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add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -expand -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
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add wave -noupdate -expand -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
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add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
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add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES
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add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN
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add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN
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add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN
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add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN
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add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
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add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
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add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
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add wave -noupdate -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
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add wave -noupdate -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
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add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
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add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
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add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
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add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
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add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
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add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
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add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES
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add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN
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add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN
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add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN
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add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN
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add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
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add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
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add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
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add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
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add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
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add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
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add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATA
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add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATAMasked
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add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATANext
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@ -242,17 +240,18 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/DataStall
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/MemPAdrM
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/ReadDataW
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/WriteDataM
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/AtomicMaskedM
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/DSquashBusAccessM
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/HRDATAW
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/MemAckW
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add wave -noupdate -group lsu /testbench/dut/hart/lsu/StallW
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemRWM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DataStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemPAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataW
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/AtomicMaskedM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DSquashBusAccessM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HRDATAW
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAckW
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/StallW
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
|
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@ -295,22 +294,26 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
|
||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/PRegEn
|
||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/WalkerState
|
||||
add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/pagetablewalker/WalkerState
|
||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUReady
|
||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/HPTWStall
|
||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/TranslationPAdr
|
||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUReadPTE
|
||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUTranslate
|
||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/HPTWRead
|
||||
add wave -noupdate -expand -group ptwalker -divider data
|
||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUPAdr
|
||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUReadPTE
|
||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/CurrentPTE
|
||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/TranslationPAdr
|
||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/ValidPTE
|
||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/LeafPTE
|
||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUStall
|
||||
add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWTranslate
|
||||
add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWPAdr
|
||||
add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWReadPTE
|
||||
add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWReady
|
||||
add wave -noupdate -group {LSU ARB} -expand -group toLSU /testbench/dut/hart/arbiter/MemAdrMtoLSU
|
||||
add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/SelPTW
|
||||
add wave -noupdate -expand -group {LSU ARB} -color Gold /testbench/dut/hart/arbiter/CurrState
|
||||
add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWTranslate
|
||||
add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWPAdr
|
||||
add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWReadPTE
|
||||
add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWReady
|
||||
add wave -noupdate -expand -group {LSU ARB} -expand -group toLSU /testbench/dut/hart/arbiter/MemAdrMtoLSU
|
||||
add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/SelPTW
|
||||
add wave -noupdate /testbench/dut/hart/lsu/DataStall
|
||||
add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
||||
add wave -noupdate /testbench/dut/uncore/genblk2/plic/ExtIntM
|
||||
@ -336,15 +339,9 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/INTR
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb
|
||||
add wave -noupdate /testbench/dut/uncore/genblk2/plic/pendingPGrouped
|
||||
add wave -noupdate /testbench/dut/uncore/genblk2/plic/intPending
|
||||
add wave -noupdate /testbench/dut/uncore/genblk2/plic/nextIntPending
|
||||
add wave -noupdate /testbench/dut/uncore/genblk2/plic/requests
|
||||
add wave -noupdate /testbench/dut/uncore/genblk2/plic/GPIOIntr
|
||||
add wave -noupdate /testbench/dut/uncore/genblk2/plic/UARTIntr
|
||||
add wave -noupdate /testbench/dut/uncore/genblk4/uart/u/intrpending
|
||||
add wave -noupdate -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 5} {9729816 ns} 0} {{Cursor 6} {7857655 ns} 0} {{Cursor 7} {7869135 ns} 1} {{Cursor 8} {7868621 ns} 0} {{Cursor 9} {7868621 ns} 0} {{Cursor 10} {7865190 ns} 0} {{Cursor 11} {7867237 ns} 0}
|
||||
WaveRestoreCursors {{Cursor 5} {11172515 ns} 0} {{Cursor 8} {9673965 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 189
|
||||
@ -360,4 +357,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {9729788 ns} {9730412 ns}
|
||||
WaveRestoreZoom {11172446 ns} {11172732 ns}
|
||||
|
||||
@ -31,6 +31,7 @@ module lsuArb
|
||||
|
||||
// from page table walker
|
||||
input logic HPTWTranslate,
|
||||
input logic HPTWRead,
|
||||
input logic [`XLEN-1:0] HPTWPAdr,
|
||||
// to page table walker.
|
||||
output logic [`XLEN-1:0] HPTWReadPTE,
|
||||
@ -82,7 +83,7 @@ module lsuArb
|
||||
|
||||
localparam StateReady = 0;
|
||||
localparam StatePTWPending = 1;
|
||||
localparam StatePTWActive = 1;
|
||||
localparam StatePTWActive = 2;
|
||||
|
||||
logic [1:0] CurrState, NextState;
|
||||
logic SelPTW;
|
||||
@ -102,11 +103,12 @@ module lsuArb
|
||||
else if (HPTWTranslate & ~DataStall) NextState = StatePTWActive;
|
||||
else NextState = StateReady;
|
||||
StatePTWPending:
|
||||
if (~DataStall) NextState = StatePTWActive;
|
||||
else NextState = StatePTWPending;
|
||||
if (HPTWTranslate & ~DataStall) NextState = StatePTWActive;
|
||||
else if (HPTWTranslate & DataStall) NextState = StatePTWPending;
|
||||
else NextState = StateReady;
|
||||
StatePTWActive:
|
||||
if (~DataStall) NextState = StateReady;
|
||||
else NextState = StatePTWActive;
|
||||
if (HPTWTranslate) NextState = StatePTWActive;
|
||||
else NextState = StateReady;
|
||||
default: NextState = StateReady;
|
||||
endcase
|
||||
end
|
||||
@ -114,8 +116,8 @@ module lsuArb
|
||||
|
||||
// multiplex the outputs to LSU
|
||||
assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
|
||||
assign SelPTW = CurrState == StatePTWActive;
|
||||
assign MemRWMtoLSU = SelPTW ? 2'b10 : MemRWM;
|
||||
assign SelPTW = (CurrState == StatePTWActive) || (CurrState == StateReady && HPTWTranslate);
|
||||
assign MemRWMtoLSU = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
|
||||
|
||||
generate
|
||||
if (`XLEN == 32) begin
|
||||
|
||||
@ -36,41 +36,42 @@
|
||||
|
||||
module pagetablewalker (
|
||||
// Control signals
|
||||
input logic clk, reset,
|
||||
input logic [`XLEN-1:0] SATP_REGW,
|
||||
input logic clk, reset,
|
||||
input logic [`XLEN-1:0] SATP_REGW,
|
||||
|
||||
// Signals from TLBs (addresses to translate)
|
||||
input logic [`XLEN-1:0] PCF, MemAdrM,
|
||||
input logic ITLBMissF, DTLBMissM,
|
||||
input logic [1:0] MemRWM,
|
||||
input logic [`XLEN-1:0] PCF, MemAdrM,
|
||||
input logic ITLBMissF, DTLBMissM,
|
||||
input logic [1:0] MemRWM,
|
||||
|
||||
// Outputs to the TLBs (PTEs to write)
|
||||
output logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM,
|
||||
output logic [1:0] PageTypeF, PageTypeM,
|
||||
output logic ITLBWriteF, DTLBWriteM,
|
||||
output logic [1:0] PageTypeF, PageTypeM,
|
||||
output logic ITLBWriteF, DTLBWriteM,
|
||||
|
||||
|
||||
|
||||
|
||||
// *** modify to send to LSU // *** KMG: These are inputs/results from the ahblite whose addresses should have already been checked, so I don't think they need to be sent through the LSU
|
||||
input logic [`XLEN-1:0] MMUReadPTE,
|
||||
input logic MMUReady,
|
||||
input logic HPTWStall,
|
||||
input logic [`XLEN-1:0] MMUReadPTE,
|
||||
input logic MMUReady,
|
||||
input logic HPTWStall,
|
||||
|
||||
// *** modify to send to LSU
|
||||
output logic [`XLEN-1:0] MMUPAdr,
|
||||
output logic MMUTranslate, // *** rename to HPTWReq
|
||||
output logic MMUTranslate, // *** rename to HPTWReq
|
||||
output logic HPTWRead,
|
||||
|
||||
|
||||
|
||||
|
||||
// Stall signal
|
||||
output logic MMUStall,
|
||||
output logic MMUStall,
|
||||
|
||||
// Faults
|
||||
output logic WalkerInstrPageFaultF,
|
||||
output logic WalkerLoadPageFaultM,
|
||||
output logic WalkerStorePageFaultM
|
||||
output logic WalkerInstrPageFaultF,
|
||||
output logic WalkerLoadPageFaultM,
|
||||
output logic WalkerStorePageFaultM
|
||||
);
|
||||
|
||||
// Internal signals
|
||||
@ -201,6 +202,9 @@ module pagetablewalker (
|
||||
assign VPN1 = TranslationVAdrQ[31:22];
|
||||
assign VPN0 = TranslationVAdrQ[21:12];
|
||||
|
||||
assign HPTWRead = (WalkerState == IDLE && MMUTranslate) ||
|
||||
WalkerState == LEVEL2 || WalkerState == LEVEL1;
|
||||
|
||||
// Assign combinational outputs
|
||||
always_comb begin
|
||||
// default values
|
||||
@ -279,6 +283,10 @@ module pagetablewalker (
|
||||
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV ||
|
||||
WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall;
|
||||
|
||||
assign HPTWRead = (WalkerState == IDLE && MMUTranslate) || WalkerState == LEVEL3 ||
|
||||
WalkerState == LEVEL2 || WalkerState == LEVEL1;
|
||||
|
||||
|
||||
always_comb begin
|
||||
case (WalkerState)
|
||||
IDLE: if (MMUTranslate && SvMode == `SV48) NextWalkerState = LEVEL3_WDV;
|
||||
|
||||
@ -131,6 +131,7 @@ module wallypipelinedhart
|
||||
logic [`XLEN-1:0] MMUPAdr, MMUReadPTE;
|
||||
logic MMUStall;
|
||||
logic MMUTranslate, MMUReady;
|
||||
logic HPTWRead;
|
||||
logic HPTWReadyfromLSU;
|
||||
logic HPTWStall;
|
||||
|
||||
@ -186,7 +187,8 @@ module wallypipelinedhart
|
||||
|
||||
mux2 #(`XLEN) OutputInput2mux(WriteDataM, FWriteDataM, FMemRWM[0], WriteDatatmpM);
|
||||
|
||||
pagetablewalker pagetablewalker(.*); // can send addresses to ahblite, send out pagetablestall
|
||||
pagetablewalker pagetablewalker(.HPTWRead(HPTWRead),
|
||||
.*); // can send addresses to ahblite, send out pagetablestall
|
||||
// *** can connect to hazard unit
|
||||
// changing from this to the line above breaks the program. auipc at 104 fails; seems to be flushed.
|
||||
// Would need to insertinstruction as InstrD, not InstrF
|
||||
@ -200,6 +202,7 @@ module wallypipelinedhart
|
||||
// arbiter between IEU and pagetablewalker
|
||||
lsuArb arbiter(// HPTW connection
|
||||
.HPTWTranslate(MMUTranslate),
|
||||
.HPTWRead(HPTWRead),
|
||||
.HPTWPAdr(MMUPAdr),
|
||||
.HPTWReadPTE(MMUReadPTE),
|
||||
.HPTWReady(MMUReady),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user