forked from Github_Repos/cvw
Add one more test to WALLY-CAUSE, and update privileged testgen
This commit is contained in:
Domenico Ottolia
parent
6619a5f44f
commit
f7cbaeb217
@ -371,6 +371,7 @@ string tests32i[] = {
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if (`A_SUPPORTED) tests = {tests, tests32a};
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end
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// tests = tests64p;
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end
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@ -1,6 +1,6 @@
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# Privileged Test Generators
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Create a test generator in this folder with the name testgen-NAME.py. Then, to generate and compile these tests, use
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Create a test generator in this folder with the name testgen-NAME.py. Then, to generate and compile these tests, use:
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```bash
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sh run.sh NAME
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@ -8,8 +8,15 @@ sh run.sh NAME
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For example, for `testgen-CAUSE.py`, we would run `sh run.sh CAUSE`.
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This bash file is super basic, so only allows for a single argument after the name.
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Provide -sim as the second argument to simulate the compiled tests using wally.
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```bash
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sh run.sh NAME -sim
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```
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To compile tests without running them in OVPsim, provide -c as the second argument
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```bash
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sh run.sh NAME -c
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```
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@ -13,13 +13,28 @@ then
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python3 "testgen-$1.py"
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printf "\n\n#####\nRan testgen-$1.py Making...\n#####\n\n\n"
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if [[ "$2" != "-nosim" ]]
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if [[ "$2" == "-c" ]]
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then
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cd ~/riscv-wally/imperas-riscv-tests/riscv-test-suite/rv64p/src
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riscv64-unknown-elf-gcc -nostdlib -nostartfiles -march=rv64g "WALLY-$1".S -I../../../riscv-test-env -I../../../riscv-test-env/p -I../../../riscv-target/riscvOVPsimPlus -T../../../riscv-test-env/p/link.ld -o "../../../work/rv64p/WALLY-$1.elf"
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cd ~/riscv-wally/imperas-riscv-tests/work/rv64p
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riscv64-unknown-elf-objdump -d "WALLY-$1".elf > "WALLY-$1".elf.objdump
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elif [[ "$2" != "-nosim" ]]
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then
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cd ~/riscv-wally/imperas-riscv-tests
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make privileged
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fi
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fi
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if [[ "$2" == "-simonly" ]]
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then
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cd ~/riscv-wally/imperas-riscv-tests/riscv-test-suite/rv64p/src
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riscv64-unknown-elf-gcc -nostdlib -nostartfiles -march=rv64g "WALLY-$1".S -I../../../riscv-test-env -I../../../riscv-test-env/p -I../../../riscv-target/riscvOVPsimPlus -T../../../riscv-test-env/p/link.ld -o "../../../work/rv64p/WALLY-$1.elf"
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cd ~/riscv-wally/imperas-riscv-tests/work/rv64p
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riscv64-unknown-elf-objdump -d "WALLY-$1".elf > "WALLY-$1".elf.objdump
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fi
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if [[ "$2" == "-sim" || "$2" == "-simonly" ]]
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then
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printf "\n\n\n#####\nSimulating!\n#####\n\n"
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@ -1,6 +1,6 @@
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#!/usr/bin/python3
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##################################
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# testgen-ADD-SUB.py
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# testgen-CAUSE.py
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#
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# dottolia@hmc.edu 1 Mar 2021
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#
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@ -19,15 +19,6 @@ from random import getrandbits
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# functions
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##################################
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# def computeExpected(a, b, test):
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# if (test == "ADD"):
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# return a + b
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# elif (test == "SUB"):
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# return a - b
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# else:
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# die("bad test name ", test)
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# # exit(1)
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def randRegs():
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reg1 = randint(1,20)
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reg2 = randint(1,20)
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@ -39,34 +30,56 @@ def randRegs():
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def writeVectors(storecmd):
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global testnum
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#expected = computeExpected(a, b, test)
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#expected = expected % 2**xlen # drop carry if necessary
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#if (expected < 0): # take twos complement
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# expected = 2**xlen + expected
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#lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
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#lines = lines + "li x" + str(reg2) + ", MASK_XLEN(0)\n"
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# Page 6 of unpriviledged spec
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# Page 6 of unpriviledged spec
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# For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects
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#lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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#lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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# User Software Interrupt: True, 0
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# Supervisor Software Interrupt: True, 1
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# Machine Software Interrupt: True, 2
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# User Timer Interrupt: True, 4
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# When running run.sh CAUSE -c, everything works, but begin_signature doesn't appear
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# writeTest(storecmd, f, r, f"""
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# la x21, 0x2004000
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# """, False, 4)
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# la x10, 0x02000000 #clint
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# li x1, 42
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# lw x1, 0(x10)
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# """, True, 2, "m", f"""
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# lw x0, 0(x10)
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# """)
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# User Timer Interrupt: True, 4
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# Supervior timer interrupt: True, 5
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# Machine timer interrupt: True, 7
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# writeTest(storecmd, f, r, f"""
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# la x10, 0x02004000 #clint timer
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# li x1, 42
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# lw x11, 0(x10)
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# lw x12, 4(x10)
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# sw x1, 0(x10)
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# sw x0, 4(x10)
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# """, True, 7, "m", f"""
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# sw x11, 0(x10)
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# sw x12, 4(x10)
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# """)
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# User external input: True, 8
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# Supervisor external input: True, 9
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# Machine externa input: True, 11
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# Instruction address misaligned: False, 0
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# looks like this is giving us an infinite loop for wally
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# BUG: jumping to a misaligned instruction address doesn't cause an exception: we actually jump...
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# Either that, or somehow at the end we always end up at 0x80004002
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# This is fine in OVPsim
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writeTest(storecmd, f, r, f"""
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li x1, 11
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li x25, 0 # Force this test to pass, for now
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# jr x1 # Something about this instruction is funky on wally, but fine with ovpsim
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""", False, 0)
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# Instruction access fault: False, 1
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# Illegal Instruction
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@ -106,7 +119,7 @@ def writeVectors(storecmd):
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# Environment call from m-mode
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writeTest(storecmd, f, r, f"""
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ecall
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""", False, 11, "m")
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""", False, 11, "m")
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# Instruction page fault: 12
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# Load page fault: 13
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@ -115,7 +128,7 @@ def writeVectors(storecmd):
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def writeTest(storecmd, f, r, test, interrupt, code, mode = "m"):
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def writeTest(storecmd, f, r, test, interrupt, code, mode = "m", resetHander = ""):
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global testnum
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expected = code
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@ -162,6 +175,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, mode = "m"):
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j _jtest{testnum}
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# Machine trap vector
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{resetHander}
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csrrs x25, mcause, x0
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csrrs x1, mepc, x0
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addi x1, x1, 4
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@ -174,6 +188,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, mode = "m"):
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csrrw x0, mtvec, x30
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# Start test code
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li x25, 0x7BAD
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{before}
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{test}
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@ -213,7 +228,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, mode = "m"):
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# csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci
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author = "dottolia@hmc.edu"
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xlens = [32, 64]
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numrand = 30;
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numrand = 15;
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# setup
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seed(0xC365DDEB9173AB42) # make tests reproducible
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