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Added Ross's addr lab stuff to coremark stuff

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This commit is contained in:
Teo Ene 2021-03-17 14:50:54 -05:00
parent 041439c008
commit dfe6df2e00
1 changed files with 8 additions and 1 deletions
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9
wally-pipelined/testbench/testbench-coremark_bare.sv
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@ -76,6 +76,8 @@ module testbench();
$readmemh(memfilename, dut.uncore.dtim.RAM);
for(j=2371; j < 65535; j = j+1)
dut.uncore.dtim.RAM[j] = 64'b0;
ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.addr";
ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.lab";
reset = 1; # 22; reset = 0;
end
// generate clock to sequence tests
@ -92,11 +94,16 @@ module testbench();
end
end
if (1 == 1) begin : functionRadix
function_radix function_radix(.reset(reset),
.ProgramAddrMapFile(ProgramAddrMapFile),
.ProgramLabelMapFile(ProgramLabelMapFile));
end
initial begin
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.DirPredictor.memory.memory);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
end
endmodule
/* verilator lint_on STMTDLY */