forked from Github_Repos/cvw
Merge branch 'walker' into main
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commit
3303a013ef
@ -89,8 +89,8 @@ module ahblite (
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else BusState <= #1 NextBusState;
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always_comb
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case (BusState)
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IDLE: if (MemReadM) NextBusState = MEMREAD; // Memory has pirority over instructions
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case (BusState)
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IDLE: if (MemReadM) NextBusState = MEMREAD; // Memory has priority over instructions
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else if (MemWriteM) NextBusState = MEMWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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102
wally-pipelined/src/ebu/pagetablewalker.sv
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102
wally-pipelined/src/ebu/pagetablewalker.sv
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@ -0,0 +1,102 @@
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///////////////////////////////////////////
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// ahblite.sv
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//
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// Written: tfleming@hmc.edu 2 March 2021
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// Modified:
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//
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// Purpose: Page Table Walker
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// Part of the Memory Management Unit (MMU)
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module pagetablewalker (
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input logic clk, reset,
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input logic [`XLEN-1:0] satp,
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input logic TLBMissF,
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input logic [`XLEN-1:0] TranslationVAdr,
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input logic HCLK, HRESETn,
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input logic HREADY,
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output logic [`XLEN-1:0] PageTableEntryF,
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output logic TranslationComplete
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);
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/*
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generate
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if (`XLEN == 32) begin
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logic Sv_Mode = satp[31]
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end else begin
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logic Sv_Mode [3:0] = satp[63:60]
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end
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endgenerate
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*/
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logic Sv_Mode = satp[31];
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logic BasePageTablePPN [21:0] = satp[21:0];
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logic VPN1 [9:0] = TranslationVAdr[31:22];
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logic VPN0 [9:0] = TranslationVAdr[21:12]; // *** could optimize by not passing offset?
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logic TranslationPAdr [33:0];
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typedef enum {IDLE, LEVEL1, LEVEL0, LEAF, FAULT} statetype;
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statetype WalkerState, NextWalkerState;
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) WalkerState <= #1 IDLE;
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else WalkerState <= #1 NextWalkerState;
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always_comb begin
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NextWalkerState = 'X;
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case (WalkerState)
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IDLE: if (TLBMissM) NextWalkerState = LEVEL1;
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else NextWalkerState = IDLE;
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LEVEL1: if (HREADY && ValidEntry) NextWalkerState = LEVEL0;
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else if (HREADY) NextWalkerState = FAULT;
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else NextWalkerState = LEVEL1;
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LEVEL2: if (HREADY && ValidEntry) NextWalkerState = LEAF;
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else if (HREADY) NextWalkerState = FAULT;
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else NextWalkerState = LEVEL2;
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LEAF: NextWalkerState = IDLE;
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endcase
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end
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin
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TranslationPAdr <= '0;
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PageTableEntryF <= '0;
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TranslationComplete <= '0;
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end else begin
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// default values
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case (NextWalkerState)
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LEVEL1: TranslationPAdr <= {BasePageTablePPN, VPN1, 2'b00};
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LEVEL2: TranslationPAdr <= {CurrentPPN, VPN0, 2'b00};
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LEAF: PageTableEntryF <= CurrentPageTableEntry;
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TranslationComplete <= '1;
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end
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assign #1 Translate = (NextWalkerState = LEVEL1);
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endmodule
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