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busybear: preload bootram

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thanks to Prof Stine for the .do file commands

@kaveh can you check line 201? it does nothing, but things break when
I remove that line
This commit is contained in:
Noah Boorstin 2021-02-24 18:44:50 +00:00
parent b36a5614b4
commit 3d82ceffb7
2 changed files with 9 additions and 4 deletions
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3
wally-pipelined/regression/wally-busybear.do
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@ -27,11 +27,14 @@ vlib work-busybear
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt +acc work.testbench_busybear -o workopt
vsim workopt -suppress 8852,12070
mem load -startaddress 0 -endaddress 1024 -filltype value -fillradix hex -filldata 0 /testbench_busybear/bootram
mem load -startaddress 0 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/bootram
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10
wally-pipelined/testbench/testbench-busybear.sv
View File

@ -177,7 +177,8 @@ module testbench_busybear();
logic [`XLEN-1:0] RAM[('h8000000 >> 3):0];
logic [`XLEN-1:0] bootram[('h2000 >> 3):0];
logic [`XLEN-1:0] readRAM, readPC;
logic [`XLEN-1:0] readRAM;
logic [31:0] readPC;
integer RAMAdr, RAMPC;
assign RAMAdr = (HADDR - (HADDR > 'h2fff ? 'h80000000 : 'h1000)) >> 3;
assign RAMPC = (PCF - (PCF > 'h2fff ? 'h80000000 : 'h1000)) >> 3;
@ -194,7 +195,7 @@ module testbench_busybear();
end
always @(PCF) begin
if (PCF >= 'h80000000 && PCF <= 'h87FFFFFF) begin
readPC = RAM[RAMPC];
readPC = RAM[RAMPC] >> PCF[2] * 32;
end
end
// there's almost certianly a better way than just copying this, but its simple enough for now:
@ -208,8 +209,9 @@ module testbench_busybear();
end
end
always @(PCF) begin
$write(""); // I know this does nothing, the first instruction doesn't load for me without it
if (PCF >= 'h1000 && PCF <= 'h2FFF) begin
readPC = bootram[RAMPC];
readPC = bootram[RAMPC] >> PCF[2] * 32;
end
end
@ -431,7 +433,7 @@ module testbench_busybear();
$display("%0t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, PCF, pcExpected);
`ERROR
end
if (readPC != InstrF) begin
if ((~speculative) && (readPC != InstrF)) begin
$display("%0t ps, instr %0d: readPC does not equal InstrF: %x, %x", $time, instrs, readPC, InstrF);
warningCount += 1;
end