forked from Github_Repos/cvw
Don't use this branch walker still broken.
This commit is contained in:
Ross Thompson
parent
d80ebab941
commit
bc9c944ba0
@ -218,9 +218,11 @@ add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/har
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemReadM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemWriteM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemSizeM
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATANext
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HREADY
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESP
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDR
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@ -234,9 +236,12 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -expand -group lsu /testbench/dut/hart/arbiter/MemAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DataStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemPAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataW
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/AtomicMaskedM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DSquashBusAccessM
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@ -282,8 +287,25 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/PRegEn
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/WalkerState
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUReady
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/HPTWStall
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/TranslationPAdr
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUReadPTE
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUPAdr
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/CurrentPTE
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/ValidPTE
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/LeafPTE
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add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWTranslate
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add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWPAdr
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add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWReadPTE
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add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/HPTWReady
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add wave -noupdate -expand -group {LSU ARB} -expand -group toLSU /testbench/dut/hart/arbiter/MemAdrMtoLSU
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add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/SelPTW
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add wave -noupdate /testbench/dut/hart/lsu/DataStall
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {11165332 ns} 0} {{Cursor 3} {7672141 ns} 0}
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WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {11172098 ns} 0} {{Cursor 3} {7672141 ns} 0}
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quietly wave cursor active 2
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 189
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@ -299,4 +321,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {11156770 ns} {11173894 ns}
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WaveRestoreZoom {11171939 ns} {11172253 ns}
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@ -29,71 +29,73 @@
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// *** Ross Thompson amo misalignment check?
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module lsu (
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input logic clk, reset,
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input logic StallM, FlushM, StallW, FlushW,
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output logic DataStall,
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output logic HPTWReady,
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input logic clk, reset,
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input logic StallM, FlushM, StallW, FlushW,
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output logic DataStall,
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output logic HPTWReady,
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// Memory Stage
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// connected to cpu (controls)
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input logic [1:0] MemRWM,
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input logic [2:0] Funct3M,
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input logic [1:0] AtomicM,
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output logic CommittedM,
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output logic SquashSCW,
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output logic DataMisalignedM,
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input logic [1:0] MemRWM,
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input logic [2:0] Funct3M,
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input logic [1:0] AtomicM,
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output logic CommittedM,
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output logic SquashSCW,
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output logic DataMisalignedM,
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// address and write data
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input logic [`XLEN-1:0] MemAdrM,
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input logic [`XLEN-1:0] WriteDataM,
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output logic [`XLEN-1:0] ReadDataW, // from ahb
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input logic [`XLEN-1:0] MemAdrM,
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input logic [`XLEN-1:0] WriteDataM,
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output logic [`XLEN-1:0] ReadDataW,
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// cpu privilege
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input logic [1:0] PrivilegeModeW,
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input logic DTLBFlushM,
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input logic [1:0] PrivilegeModeW,
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input logic DTLBFlushM,
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// faults
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input logic NonBusTrapM,
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output logic DTLBLoadPageFaultM, DTLBStorePageFaultM,
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output logic LoadMisalignedFaultM, LoadAccessFaultM,
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input logic NonBusTrapM,
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output logic DTLBLoadPageFaultM, DTLBStorePageFaultM,
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output logic LoadMisalignedFaultM, LoadAccessFaultM,
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// cpu hazard unit (trap)
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output logic StoreMisalignedFaultM, StoreAccessFaultM,
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output logic StoreMisalignedFaultM, StoreAccessFaultM,
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// connect to ahb
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input logic CommitM, // should this be generated in the abh interface?
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output logic [`PA_BITS-1:0] MemPAdrM, // to ahb
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output logic MemReadM, MemWriteM,
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output logic [1:0] AtomicMaskedM,
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input logic MemAckW, // from ahb
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input logic [`XLEN-1:0] HRDATAW, // from ahb
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input logic CommitM, // should this be generated in the abh interface?
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output logic [`PA_BITS-1:0] MemPAdrM, // to ahb
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output logic MemReadM, MemWriteM,
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output logic [1:0] AtomicMaskedM,
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input logic MemAckW, // from ahb
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input logic [`XLEN-1:0] HRDATAW, // from ahb
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output logic [2:0] Funct3MfromLSU,
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output logic StallWfromLSU,
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// mmu management
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// page table walker
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input logic [`XLEN-1:0] PageTableEntryM,
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input logic [1:0] PageTypeM,
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input logic [`XLEN-1:0] SATP_REGW, // from csr
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input logic STATUS_MXR, STATUS_SUM, // from csr
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input logic DTLBWriteM,
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output logic DTLBMissM,
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input logic DisableTranslation, // used to stop intermediate PTE physical addresses being saved to TLB.
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input logic [`XLEN-1:0] PageTableEntryM,
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input logic [1:0] PageTypeM,
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input logic [`XLEN-1:0] SATP_REGW, // from csr
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input logic STATUS_MXR, STATUS_SUM, // from csr
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input logic DTLBWriteM,
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output logic DTLBMissM,
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input logic DisableTranslation, // used to stop intermediate PTE physical addresses being saved to TLB.
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output logic DTLBHitM, // not connected
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output logic DTLBHitM, // not connected
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// PMA/PMP (inside mmu) signals
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input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well.
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input logic [2:0] HSIZE,
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input logic HWRITE,
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input logic AtomicAccessM, WriteAccessM, ReadAccessM, // execute access is hardwired to zero in this mmu because we're only working with data in the M stage.
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input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker.
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input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well.
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input logic [2:0] HSIZE,
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input logic HWRITE,
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input logic AtomicAccessM, WriteAccessM, ReadAccessM, // execute access is hardwired to zero in this mmu because we're only working with data in the M stage.
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input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker.
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output logic PMALoadAccessFaultM, PMAStoreAccessFaultM,
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output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa.
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output logic PMALoadAccessFaultM, PMAStoreAccessFaultM,
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output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa.
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output logic DSquashBusAccessM
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output logic DSquashBusAccessM
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// output logic [5:0] DHSELRegionsM
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);
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@ -246,13 +248,15 @@ module lsu (
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end
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end
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STATE_FETCH: begin
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DataStall = 1'b1;
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if (MemAckW & ~StallW) begin
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NextState = STATE_READY;
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DataStall = 1'b0;
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end else if (MemAckW & StallW) begin
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NextState = STATE_STALLED;
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DataStall = 1'b1;
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end else begin
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NextState = STATE_FETCH;
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DataStall = 1'b1;
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end
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end
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STATE_STALLED: begin
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@ -268,7 +272,12 @@ module lsu (
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NextState = STATE_READY;
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end
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endcase
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end
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end // always_comb
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// *** for now just pass through size
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assign Funct3MfromLSU = Funct3M;
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assign StallWfromLSU = StallW;
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endmodule
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@ -35,6 +35,7 @@ module lsuArb
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// to page table walker.
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output logic [`XLEN-1:0] HPTWReadPTE,
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output logic HPTWReady,
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output logic HPTWStall,
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// from CPU
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input logic [1:0] MemRWM,
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@ -42,6 +43,7 @@ module lsuArb
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input logic [1:0] AtomicM,
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input logic [`XLEN-1:0] MemAdrM,
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input logic [`XLEN-1:0] WriteDataM,
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input logic StallW,
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// to CPU
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output logic [`XLEN-1:0] ReadDataW,
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output logic CommittedM,
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@ -56,12 +58,13 @@ module lsuArb
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output logic [1:0] AtomicMtoLSU,
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output logic [`XLEN-1:0] MemAdrMtoLSU,
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output logic [`XLEN-1:0] WriteDataMtoLSU,
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output logic StallWtoLSU,
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// from LSU
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input logic CommittedMfromLSU,
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input logic SquashSCWfromLSU,
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input logic DataMisalignedMfromLSU,
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input logic [`XLEN-1:0] ReadDataWFromLSU,
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input logic HPTWReadyfromLSU,
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input logic HPTWReadyfromLSU,
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input logic DataStall
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);
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@ -124,6 +127,7 @@ module lsuArb
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assign AtomicMtoLSU = SelPTW ? 2'b00 : AtomicM;
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assign MemAdrMtoLSU = SelPTW ? HPTWPAdr : MemAdrM;
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assign WriteDataMtoLSU = SelPTW ? `XLEN'b0 : WriteDataM;
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assign StallWtoLSU = SelPTW ? 1'b0 : StallW;
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// demux the inputs from LSU to walker or cpu's data port.
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@ -133,6 +137,10 @@ module lsuArb
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assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromLSU;
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assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromLSU;
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assign HPTWReady = HPTWReadyfromLSU;
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assign DCacheStall = DataStall; // *** this is probably going to change.
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// *** need to rename DcacheStall and Datastall.
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// not clear at all. I think it should be LSUStall from the LSU,
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// which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
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assign HPTWStall = SelPTW ? DataStall : 1'b1;
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assign DCacheStall = SelPTW ? 1'b0 : DataStall; // *** this is probably going to change.
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endmodule
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@ -55,6 +55,7 @@ module pagetablewalker (
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// *** modify to send to LSU // *** KMG: These are inputs/results from the ahblite whose addresses should have already been checked, so I don't think they need to be sent through the LSU
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input logic [`XLEN-1:0] MMUReadPTE,
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input logic MMUReady,
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input logic HPTWStall,
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// *** modify to send to LSU
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output logic [`XLEN-1:0] MMUPAdr,
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@ -140,14 +141,22 @@ module pagetablewalker (
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assign PageTypeF = PageType;
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assign PageTypeM = PageType;
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localparam LEVEL0 = 3'h0;
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localparam LEVEL1 = 3'h1;
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localparam LEVEL0_WDV = 4'h0;
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localparam LEVEL0 = 4'h8;
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localparam LEVEL1_WDV = 4'h1;
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localparam LEVEL1 = 4'h9;
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localparam LEVEL2_WDV = 4'h2;
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localparam LEVEL2 = 4'hA;
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localparam LEVEL3_WDV = 4'h3;
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localparam LEVEL3 = 4'hB;
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// space left for more levels
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localparam LEAF = 3'h5;
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localparam IDLE = 3'h6;
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localparam FAULT = 3'h7;
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localparam LEAF = 4'h5;
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localparam IDLE = 4'h6;
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localparam FAULT = 4'h7;
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logic [2:0] WalkerState, NextWalkerState;
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logic [3:0] WalkerState, NextWalkerState;
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logic PRegEn;
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generate
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if (`XLEN == 32) begin
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@ -155,27 +164,32 @@ localparam LEVEL0 = 3'h0;
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flopenl #(3) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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assign PRegEn = (WalkerState == LEVEL1 || WalkerState == LEVEL0) && ~HPTWStall;
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// State transition logic
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always_comb begin
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case (WalkerState)
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IDLE: if (MMUTranslate) NextWalkerState = LEVEL1;
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IDLE: if (MMUTranslate) NextWalkerState = LEVEL1_WDV;
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else NextWalkerState = IDLE;
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LEVEL1: if (~MMUReady) NextWalkerState = LEVEL1;
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LEVEL1_WDV: if (HPTWStall) NextWalkerState = LEVEL1_WDV;
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else NextWalkerState = LEVEL1;
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LEVEL1:
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// *** <FUTURE WORK> According to the architecture, we should
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// fault upon finding a superpage that is misaligned or has 0
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// access bit. The following commented line of code is
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// supposed to perform that check. However, it is untested.
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else if (ValidPTE && LeafPTE && ~BadMegapage) NextWalkerState = LEAF;
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if (ValidPTE && LeafPTE && ~BadMegapage) NextWalkerState = LEAF;
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
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else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0;
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else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0_WDV;
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else NextWalkerState = FAULT;
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LEVEL0: if (~MMUReady) NextWalkerState = LEVEL0;
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else if (ValidPTE && LeafPTE && ~AccessAlert)
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LEVEL0_WDV: if (HPTWStall) NextWalkerState = LEVEL0_WDV;
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else NextWalkerState = LEVEL0;
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LEVEL0: if (ValidPTE && LeafPTE && ~AccessAlert)
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NextWalkerState = LEAF;
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else NextWalkerState = FAULT;
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LEAF: if (MMUTranslate) NextWalkerState = LEVEL1;
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LEAF: if (MMUTranslate) NextWalkerState = LEVEL1_WDV;
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else NextWalkerState = IDLE;
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FAULT: if (MMUTranslate) NextWalkerState = LEVEL1;
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FAULT: if (MMUTranslate) NextWalkerState = LEVEL1_WDV;
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else NextWalkerState = IDLE;
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// Default case should never happen, but is included for linter.
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default: NextWalkerState = IDLE;
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@ -201,7 +215,7 @@ localparam LEVEL0 = 3'h0;
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WalkerLoadPageFaultM = '0;
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WalkerStorePageFaultM = '0;
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MMUStall = '1;
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case (NextWalkerState)
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IDLE: begin
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MMUStall = '0;
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@ -209,9 +223,15 @@ localparam LEVEL0 = 3'h0;
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LEVEL1: begin
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TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
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end
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LEVEL1_WDV: begin
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TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
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end
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LEVEL0: begin
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TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
|
||||
end
|
||||
LEVEL0_WDV: begin
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
|
||||
end
|
||||
LEAF: begin
|
||||
// Keep physical address alive to prevent HADDR dropping to 0
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
|
||||
@ -233,9 +253,16 @@ localparam LEVEL0 = 3'h0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// Capture page table entry from ahblite
|
||||
flopenr #(32) ptereg(clk, reset, MMUReady, MMUReadPTE, SavedPTE);
|
||||
mux2 #(32) ptemux(SavedPTE, MMUReadPTE, MMUReady, CurrentPTE);
|
||||
// Capture page table entry from data cache
|
||||
// *** may need to delay reading this value until the next clock cycle.
|
||||
// The clk to q latency of the SRAM in the data cache will be long.
|
||||
// I cannot see directly using this value. This is no different than
|
||||
// a load delay hazard. This will require rewriting the walker fsm.
|
||||
// also need a new signal to save. Should be a mealy output of the fsm
|
||||
// request followed by ~stall.
|
||||
flopenr #(32) ptereg(clk, reset, PRegEn, MMUReadPTE, SavedPTE);
|
||||
//mux2 #(32) ptemux(SavedPTE, MMUReadPTE, PRegEn, CurrentPTE);
|
||||
assign CurrentPTE = SavedPTE;
|
||||
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
|
||||
|
||||
// Assign outputs to ahblite
|
||||
@ -244,61 +271,70 @@ localparam LEVEL0 = 3'h0;
|
||||
assign MMUPAdr = TranslationPAdr[31:0];
|
||||
|
||||
end else begin
|
||||
localparam LEVEL2 = 3'h2;
|
||||
localparam LEVEL3 = 3'h3;
|
||||
|
||||
logic [8:0] VPN3, VPN2, VPN1, VPN0;
|
||||
|
||||
logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage;
|
||||
|
||||
flopenl #(3) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
|
||||
flopenl #(4) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
|
||||
|
||||
assign PRegEn = (WalkerState == LEVEL1 || WalkerState == LEVEL0 ||
|
||||
WalkerState == LEVEL2 || WalkerState == LEVEL3) && ~HPTWStall;
|
||||
|
||||
always_comb begin
|
||||
case (WalkerState)
|
||||
IDLE: if (MMUTranslate && SvMode == `SV48) NextWalkerState = LEVEL3;
|
||||
else if (MMUTranslate && SvMode == `SV39) NextWalkerState = LEVEL2;
|
||||
IDLE: if (MMUTranslate && SvMode == `SV48) NextWalkerState = LEVEL3_WDV;
|
||||
else if (MMUTranslate && SvMode == `SV39) NextWalkerState = LEVEL2_WDV;
|
||||
else NextWalkerState = IDLE;
|
||||
|
||||
LEVEL3: if (~MMUReady) NextWalkerState = LEVEL3;
|
||||
LEVEL3_WDV: if (HPTWStall) NextWalkerState = LEVEL3_WDV;
|
||||
else NextWalkerState = LEVEL3;
|
||||
LEVEL3:
|
||||
// *** <FUTURE WORK> According to the architecture, we should
|
||||
// fault upon finding a superpage that is misaligned or has 0
|
||||
// access bit. The following commented line of code is
|
||||
// supposed to perform that check. However, it is untested.
|
||||
else if (ValidPTE && LeafPTE && ~BadTerapage) NextWalkerState = LEAF;
|
||||
if (ValidPTE && LeafPTE && ~BadTerapage) NextWalkerState = LEAF;
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||
else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL2;
|
||||
else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL2_WDV;
|
||||
else NextWalkerState = FAULT;
|
||||
|
||||
LEVEL2: if (~MMUReady) NextWalkerState = LEVEL2;
|
||||
LEVEL2_WDV: if (HPTWStall) NextWalkerState = LEVEL2_WDV;
|
||||
else NextWalkerState = LEVEL2;
|
||||
LEVEL2:
|
||||
// *** <FUTURE WORK> According to the architecture, we should
|
||||
// fault upon finding a superpage that is misaligned or has 0
|
||||
// access bit. The following commented line of code is
|
||||
// supposed to perform that check. However, it is untested.
|
||||
else if (ValidPTE && LeafPTE && ~BadGigapage) NextWalkerState = LEAF;
|
||||
if (ValidPTE && LeafPTE && ~BadGigapage) NextWalkerState = LEAF;
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||
else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL1;
|
||||
else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL1_WDV;
|
||||
else NextWalkerState = FAULT;
|
||||
|
||||
LEVEL1: if (~MMUReady) NextWalkerState = LEVEL1;
|
||||
LEVEL1_WDV: if (HPTWStall) NextWalkerState = LEVEL1_WDV;
|
||||
else NextWalkerState = LEVEL1;
|
||||
LEVEL1:
|
||||
// *** <FUTURE WORK> According to the architecture, we should
|
||||
// fault upon finding a superpage that is misaligned or has 0
|
||||
// access bit. The following commented line of code is
|
||||
// supposed to perform that check. However, it is untested.
|
||||
else if (ValidPTE && LeafPTE && ~BadMegapage) NextWalkerState = LEAF;
|
||||
if (ValidPTE && LeafPTE && ~BadMegapage) NextWalkerState = LEAF;
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||
else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0;
|
||||
else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0_WDV;
|
||||
else NextWalkerState = FAULT;
|
||||
|
||||
LEVEL0: if (~MMUReady) NextWalkerState = LEVEL0;
|
||||
else if (ValidPTE && LeafPTE && ~AccessAlert) NextWalkerState = LEAF;
|
||||
LEVEL0_WDV: if (HPTWStall) NextWalkerState = LEVEL0_WDV;
|
||||
else NextWalkerState = LEVEL0;
|
||||
LEVEL0:
|
||||
if (ValidPTE && LeafPTE && ~AccessAlert) NextWalkerState = LEAF;
|
||||
else NextWalkerState = FAULT;
|
||||
|
||||
LEAF: if (MMUTranslate && SvMode == `SV48) NextWalkerState = LEVEL3;
|
||||
else if (MMUTranslate && SvMode == `SV39) NextWalkerState = LEVEL2;
|
||||
LEAF: if (MMUTranslate && SvMode == `SV48) NextWalkerState = LEVEL3_WDV;
|
||||
else if (MMUTranslate && SvMode == `SV39) NextWalkerState = LEVEL2_WDV;
|
||||
else NextWalkerState = IDLE;
|
||||
|
||||
FAULT: if (MMUTranslate && SvMode == `SV48) NextWalkerState = LEVEL3;
|
||||
else if (MMUTranslate && SvMode == `SV39) NextWalkerState = LEVEL2;
|
||||
FAULT: if (MMUTranslate && SvMode == `SV48) NextWalkerState = LEVEL3_WDV;
|
||||
else if (MMUTranslate && SvMode == `SV39) NextWalkerState = LEVEL2_WDV;
|
||||
else NextWalkerState = IDLE;
|
||||
// Default case should never happen, but is included for linter.
|
||||
default: NextWalkerState = IDLE;
|
||||
@ -346,15 +382,29 @@ localparam LEVEL0 = 3'h0;
|
||||
// *** this is a huge breaking point. if we're going through level3 every time, even when sv48 is off,
|
||||
// what should translationPAdr be when level3 is just off?
|
||||
end
|
||||
LEVEL3_WDV: begin
|
||||
TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
|
||||
// *** this is a huge breaking point. if we're going through level3 every time, even when sv48 is off,
|
||||
// what should translationPAdr be when level3 is just off?
|
||||
end
|
||||
LEVEL2: begin
|
||||
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
|
||||
end
|
||||
LEVEL2_WDV: begin
|
||||
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
|
||||
end
|
||||
LEVEL1: begin
|
||||
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
||||
end
|
||||
LEVEL1_WDV: begin
|
||||
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
||||
end
|
||||
LEVEL0: begin
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
end
|
||||
LEVEL0_WDV: begin
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
end
|
||||
LEAF: begin
|
||||
// Keep physical address alive to prevent HADDR dropping to 0
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
@ -380,8 +430,9 @@ localparam LEVEL0 = 3'h0;
|
||||
end
|
||||
|
||||
// Capture page table entry from ahblite
|
||||
flopenr #(`XLEN) ptereg(clk, reset, MMUReady, MMUReadPTE, SavedPTE);
|
||||
mux2 #(`XLEN) ptemux(SavedPTE, MMUReadPTE, MMUReady, CurrentPTE);
|
||||
flopenr #(`XLEN) ptereg(clk, reset, PRegEn, MMUReadPTE, SavedPTE);
|
||||
//mux2 #(`XLEN) ptemux(SavedPTE, MMUReadPTE, PRegEn, CurrentPTE);
|
||||
assign CurrentPTE = SavedPTE;
|
||||
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
|
||||
|
||||
// Assign outputs to ahblite
|
||||
|
||||
@ -136,7 +136,7 @@ module tlb #(parameter ENTRY_BITS = 3,
|
||||
endgenerate
|
||||
|
||||
// Whether translation should occur
|
||||
assign Translate = (SvMode != `NO_TRANSLATE) & (PrivilegeModeW != `M_MODE);
|
||||
assign Translate = (SvMode != `NO_TRANSLATE) & (PrivilegeModeW != `M_MODE) & ~ DisableTranslation;
|
||||
|
||||
// Determine how the TLB is currently being used
|
||||
// Note that we use ReadAccess for both loads and instruction fetches
|
||||
|
||||
@ -132,6 +132,7 @@ module wallypipelinedhart
|
||||
logic MMUStall;
|
||||
logic MMUTranslate, MMUReady;
|
||||
logic HPTWReadyfromLSU;
|
||||
logic HPTWStall;
|
||||
|
||||
|
||||
// bus interface to dmem
|
||||
@ -171,6 +172,9 @@ module wallypipelinedhart
|
||||
logic CommittedMfromLSU;
|
||||
logic SquashSCWfromLSU;
|
||||
logic DataMisalignedMfromLSU;
|
||||
logic StallWtoLSU;
|
||||
logic StallWfromLSU;
|
||||
logic [2:0] Funct3MfromLSU;
|
||||
|
||||
|
||||
|
||||
@ -199,11 +203,13 @@ module wallypipelinedhart
|
||||
.HPTWPAdr(MMUPAdr),
|
||||
.HPTWReadPTE(MMUReadPTE),
|
||||
.HPTWReady(MMUReady),
|
||||
.HPTWStall(HPTWStall),
|
||||
// CPU connection
|
||||
.MemRWM(MemRWM|FMemRWM),
|
||||
.Funct3M(Funct3M),
|
||||
.AtomicM(AtomicM),
|
||||
.MemAdrM(MemAdrM),
|
||||
.StallW(StallW),
|
||||
.WriteDataM(WriteDatatmpM),
|
||||
.ReadDataW(ReadDataW),
|
||||
.CommittedM(CommittedM),
|
||||
@ -216,7 +222,8 @@ module wallypipelinedhart
|
||||
.Funct3MtoLSU(Funct3MtoLSU),
|
||||
.AtomicMtoLSU(AtomicMtoLSU),
|
||||
.MemAdrMtoLSU(MemAdrMtoLSU),
|
||||
.WriteDataMtoLSU(WriteDataMtoLSU),
|
||||
.WriteDataMtoLSU(WriteDataMtoLSU),
|
||||
.StallWtoLSU(StallWtoLSU),
|
||||
.CommittedMfromLSU(CommittedMfromLSU),
|
||||
.SquashSCWfromLSU(SquashSCWfromLSU),
|
||||
.DataMisalignedMfromLSU(DataMisalignedMfromLSU),
|
||||
@ -232,6 +239,7 @@ module wallypipelinedhart
|
||||
.MemAdrM(MemAdrMtoLSU),
|
||||
.WriteDataM(WriteDataMtoLSU),
|
||||
.ReadDataW(ReadDataWFromLSU),
|
||||
.StallW(StallWtoLSU),
|
||||
|
||||
.CommittedM(CommittedMfromLSU),
|
||||
.SquashSCW(SquashSCWfromLSU),
|
||||
@ -239,16 +247,19 @@ module wallypipelinedhart
|
||||
.DisableTranslation(DisableTranslation),
|
||||
|
||||
.DataStall(DataStall),
|
||||
.HPTWReady(HPTWReadyfromLSU),
|
||||
.HPTWReady(HPTWReadyfromLSU),
|
||||
.Funct3MfromLSU(Funct3MfromLSU),
|
||||
.StallWfromLSU(StallWfromLSU),
|
||||
.* ); // data cache unit
|
||||
|
||||
ahblite ebu(
|
||||
//.InstrReadF(1'b0),
|
||||
//.InstrRData(InstrF), // hook up InstrF later
|
||||
.WriteDataM(WriteDatatmpM),
|
||||
.MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]),
|
||||
.MemSizeM(Funct3MfromLSU[1:0]), .UnsignedLoadM(Funct3MfromLSU[2]),
|
||||
.Funct7M(InstrM[31:25]),
|
||||
.HRDATAW(HRDATAW),
|
||||
.StallW(StallWfromLSU),
|
||||
.*);
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user