Fixed synthesis bug with icache valid bit.

2021-05-04 13:03:08 -05:00 · 2021-05-04 13:03:08 -05:00 · 21acc45121
commit 21acc45121
parent 52e4c49bbb
1 changed files with 3 additions and 1 deletions
--- a/wally-pipelined/src/ifu/icacheMem.sv
+++ b/wally-pipelined/src/ifu/icacheMem.sv
@ -89,7 +89,9 @@ module rodirectmappedmemre #(parameter NUMLINES=512, parameter LINESIZE = 256, p

    // Correctly handle the valid bits
    always_ff @(posedge clk, posedge reset) begin
-        if (reset || flush) begin
+        if (reset) begin
+            ValidOut <= {NUMLINES{1'b0}};
+        end else if (flush) begin
            ValidOut <= {NUMLINES{1'b0}};
        end else begin
            if (WriteEnable) begin