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peripheral lint fixes

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bbracker 2021-06-10 10:19:10 -04:00
parent d4aeb1c387
commit f272cd46d8
2 changed files with 7 additions and 7 deletions
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12
wally-pipelined/src/uncore/plic.sv
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@ -118,12 +118,12 @@ module plic (
24'h002004: intEn[N:32] <= #1 Din[31:0];
`endif
24'h200000: intThreshold[2:0] <= #1 Din[2:0];
24'h200004: intInProgress <= #1 intInProgress & ~(1'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion
24'h200004: intInProgress <= #1 intInProgress & ~(4'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion
endcase
// reading
if (memread)
casez(entry)
24'h0000??: Dout <= #1 {{(`XLEN-3){1'b0}},intPriority[entry[7:2]]};
24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]};
`ifdef PLIC_NUM_SRC_LT_32
24'h001000: Dout <= #1 {{(31-N){1'b0}},intPending[N:1],1'b0};
24'h002000: Dout <= #1 {{(31-N){1'b0}},intEn[N:1],1'b0};
@ -137,7 +137,7 @@ module plic (
24'h200000: Dout <= #1 {29'b0,intThreshold[2:0]};
24'h200004: begin
Dout <= #1 {26'b0,intClaim};
intInProgress <= #1 intInProgress | (1'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed
intInProgress <= #1 intInProgress | (4'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed
end
default: Dout <= #1 32'hdeadbeef; // invalid access
endcase
@ -159,8 +159,8 @@ module plic (
// pending updates
// *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered)
assign nextIntPending = (intPending | (requests & ~intInProgress)) // requests should raise intPending except when their service routine is already in progress
& ~(((entry == 24'h200004) && memread) << (intClaim-1)); // clear pending bit when claim register is read
assign nextIntPending = (intPending | (requests & ~intInProgress)) & // requests should raise intPending except when their service routine is already in progress
~({4{((entry == 24'h200004) & memread)}} << (intClaim-1)); // clear pending bit when claim register is read
flopr #(N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
// pending array - indexed by priority_lvl x source_ID
@ -207,7 +207,7 @@ module plic (
always_comb begin
intClaim = 6'b0;
for(j=N; j>0; j=j-1) begin
if(pendingRequestsAtMaxP[j]) intClaim = j;
if(pendingRequestsAtMaxP[j]) intClaim = j[5:0];
end
end

2
wally-pipelined/src/uncore/uartPC16550D.sv
View File

@ -455,7 +455,7 @@ module uartPC16550D(
assign squashRXerrIP = (prevSquashRXerrIP | setSquashRXerrIP) & ~resetSquashRXerrIP;
flopr #(1) squashRXerrIPreg(HCLK, ~HRESETn, squashRXerrIP, prevSquashRXerrIP);
// Side effect of reading IIR is lowering THRE_IP if most significant intr
assign setSquashTHRE_IP = ~MEMRb & (A==3'b010) & (intrID==2'h1); // there's a 1-cycle delay on set squash so that THRE_IP doesn't change during the process of reading IIR (otherwise combinational loop)
assign setSquashTHRE_IP = ~MEMRb & (A==3'b010) & (intrID==3'h1); // there's a 1-cycle delay on set squash so that THRE_IP doesn't change during the process of reading IIR (otherwise combinational loop)
assign resetSquashTHRE_IP = ~THRE;
assign squashTHRE_IP = prevSquashTHRE_IP & ~resetSquashTHRE_IP;
flopr #(1) squashTHRE_IPreg(HCLK, ~HRESETn, squashTHRE_IP | setSquashTHRE_IP, prevSquashTHRE_IP);