forked from Github_Repos/cvw
busybear: more adapting to new memory system
This commit is contained in:
Noah Boorstin
parent
26d4024b33
commit
4833b36535
@ -37,8 +37,10 @@ mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -fillda
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mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/uncore/bootdtim/RAM
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mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/bootram
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mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/imem/bootram
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mem load -startaddress 0 -endaddress 16777216 -filltype value -fillradix hex -filldata 0 /testbench_busybear/RAM
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mem load -startaddress 0 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/RAM
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mem load -startaddress 268435456 -endaddress 285212671 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/uncore/maindtim/RAM
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mem load -startaddress 268435456 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/dut/uncore/maindtim/RAM
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mem load -startaddress 268435456 -endaddress 285212671 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/RAM
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mem load -startaddress 268435456 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/dut/imem/RAM
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view wave
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@ -57,7 +59,12 @@ add wave /testbench_busybear/lastCheckInstrF
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add wave /testbench_busybear/speculative
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add wave /testbench_busybear/lastPC2
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add wave -divider
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add wave -hex /testbench_busybear/readRAM
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add wave /testbench_busybear/dut/uncore/HSELBootTim
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add wave /testbench_busybear/dut/uncore/HSELTim
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add wave /testbench_busybear/dut/uncore/HREADTim
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add wave /testbench_busybear/dut/uncore/maindtim/HREADTim0
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add wave /testbench_busybear/dut/uncore/HREADYTim
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add wave /testbench_busybear/dut/uncore/HADDR
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG
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@ -73,6 +80,7 @@ add wave -hex /testbench_busybear/dut/hart/MemRWM[1]
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add wave -hex /testbench_busybear/HWDATA
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add wave -hex /testbench_busybear/HRDATA
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add wave -hex /testbench_busybear/HADDR
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add wave -hex /testbench_busybear/readAdrExpected
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[1]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[2]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[3]
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@ -28,7 +28,7 @@
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module dtim #(parameter BASE=0, RANGE = 65535) (
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input logic HCLK, HRESETn,
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input logic [1:0] MemRWtim,
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input logic [18:0] HADDR,
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input logic [31:0] HADDR,
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input logic [`XLEN-1:0] HWDATA,
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input logic HSELTim,
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output logic [`XLEN-1:0] HREADTim,
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@ -36,8 +36,8 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
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);
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//logic [`XLEN-1:0] RAM[0:65535];
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logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE-BASE)>>1+(`XLEN/32)];
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logic [18:0] HWADDR;
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logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
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logic [31:0] HWADDR;
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logic [`XLEN-1:0] HREADTim0;
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// logic [`XLEN-1:0] write;
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@ -83,21 +83,21 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
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generate
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if (`XLEN == 64) begin
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// always_ff @(negedge HCLK)
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// if (memwrite) RAM[HWADDR[17:3]] <= HWDATA;
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// if (memwrite) RAM[HWADDR[31:3]] <= HWDATA;
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always_ff @(posedge HCLK) begin
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//if (memwrite) RAM[HADDR[17:3]] <= HWDATA;
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//if (memwrite) RAM[HADDR[31:3]] <= HWDATA;
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HWADDR <= HADDR;
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HREADTim0 <= RAM[HADDR[17:3]];
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if (memwrite && HREADYTim) RAM[HWADDR[17:3]] <= HWDATA;
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HREADTim0 <= RAM[HADDR[31:3]];
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if (memwrite && HREADYTim) RAM[HWADDR[31:3]] <= HWDATA;
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end
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end else begin
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// always_ff @(negedge HCLK)
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// if (memwrite) RAM[HWADDR[17:2]] <= HWDATA;
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// if (memwrite) RAM[HWADDR[31:2]] <= HWDATA;
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always_ff @(posedge HCLK) begin
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//if (memwrite) RAM[HADDR[17:2]] <= HWDATA;
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//if (memwrite) RAM[HADDR[31:2]] <= HWDATA;
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HWADDR <= HADDR;
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HREADTim0 <= RAM[HADDR[17:2]];
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if (memwrite && HREADYTim) RAM[HWADDR[17:2]] <= HWDATA;
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HREADTim0 <= RAM[HADDR[31:2]];
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if (memwrite && HREADYTim) RAM[HWADDR[31:2]] <= HWDATA;
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end
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end
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endgenerate
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@ -95,8 +95,8 @@ module uncore (
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subwordwrite sww(.*);
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// tightly integrated memory
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dtim #(.BASE(`TIMBASE), .RANGE(`TIMRANGE)) maindtim (.HADDR(HADDR[18:0]), .*);
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dtim #(.BASE(`BOOTTIMBASE), .RANGE(`BOOTTIMRANGE)) bootdtim (.HADDR(HADDR[18:0]), .MemRWtim(MemRWboottim),
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dtim #(.BASE(`TIMBASE), .RANGE(`TIMRANGE)) maindtim (.*);
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dtim #(.BASE(`BOOTTIMBASE), .RANGE(`BOOTTIMRANGE)) bootdtim (.MemRWtim(MemRWboottim),
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.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
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// memory-mapped I/O peripherals
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@ -110,11 +110,11 @@ module uncore (
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// AHB Read Multiplexer
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assign HRDATA = ({`XLEN{HSELTim}} & HREADTim) | ({`XLEN{HSELCLINT}} & HREADCLINT) |
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({`XLEN{HSELBootTim}} & HREADBootTim) | ({`XLEN{HSELUART}} & HREADUART);
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assign HRESP = HSELBootTim & HRESPBootTim | HSELTim & HRESPTim | HSELCLINT & HRESPCLINT | HSELGPIO & HRESPGPIO | HSELUART & HRESPUART;
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assign HREADY = HSELBootTim & HREADYBootTim | HSELTim & HREADYTim | HSELCLINT & HREADYCLINT | HSELGPIO & HREADYGPIO | HSELUART & HREADYUART;
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assign HRESP = HSELBootTim & HRESPBootTim | HSELTim & HRESPTim | HSELCLINT & HRESPCLINT | HSELUART & HRESPUART;
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assign HREADY = HSELBootTim & HREADYBootTim | HSELTim & HREADYTim | HSELCLINT & HREADYCLINT | HSELUART & HREADYUART;
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// Faults
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assign DataAccessFaultM = ~(HSELTim | HSELCLINT | HSELGPIO | HSELUART);
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assign DataAccessFaultM = ~(HSELTim | HSELCLINT | HSELUART);
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endmodule
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@ -174,52 +174,27 @@ module testbench_busybear();
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// In the linux boot, the processor spends the first ~5 instructions in
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// bootram, before jr jumps to main RAM
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logic [`XLEN-1:0] RAM[('h8000000 >> 3):0];
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logic [`XLEN-1:0] bootram[('h2000 >> 3):0];
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logic [`XLEN-1:0] readRAM;
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integer RAMAdr, RAMPC;
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assign RAMAdr = (HADDR - (HADDR > 'h2fff ? 'h80000000 : 'h1000)) >> 3;
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assign RAMPC = (dut.PCF - (dut.PCF > 'h2fff ? 'h80000000 : 'h1000)) >> 3;
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logic [63:0] readMask;
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assign readMask = ((1 << (8*(1 << HSIZE))) - 1) << 8 * HADDR[2:0];
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logic [`XLEN-1:0] readAdrExpected;
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always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin
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if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin
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if (HWRITE) begin
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RAM[RAMAdr] = (RAM[RAMAdr] & (~readMask)) | ((HWDATA << 8 * HADDR[2:0]) & readMask); // aligns write data for correct subword size
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end else begin
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readRAM = RAM[RAMAdr] & readMask;
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end
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end
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if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h1000 && HADDR <= 'h2FFF)) begin
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if (HWRITE) begin
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bootram[RAMAdr] = (bootram[RAMAdr] & (~readMask)) | ((HWDATA << 8 * HADDR[2:0]) & readMask);
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end else begin
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readRAM = bootram[RAMAdr] & readMask;
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end
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end
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end
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always @(dut.hart.MemRWM[1] or HADDR) begin
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if (dut.hart.MemRWM[1]) begin
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if (dut.hart.MemRWM[1] && HADDR != dut.PCF) begin
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if($feof(data_file_memR)) begin
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$display("no more memR data to read");
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`ERROR
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end
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scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
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scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA);
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#1;
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#2;
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if (~equal(HADDR,readAdrExpected,4)) begin
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$display("%0t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected);
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`ERROR
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end
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if (((readMask & HRDATA) !== (readMask & readRAM)) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin
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$display("warning %0t ps, instr %0d: HRDATA does not equal readRAM: %x, %x from address %x, %x", $time, instrs, HRDATA, readRAM, HADDR, HSIZE);
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if (((readMask & HRDATA) !== (readMask & dut.HRDATA)) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin
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$display("warning %0t ps, instr %0d: HRDATA does not equal dut.HRDATA: %x, %x from address %x, %x", $time, instrs, HRDATA, dut.HRDATA, HADDR, HSIZE);
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warningCount += 1;
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`ERROR
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end
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@ -360,79 +335,81 @@ module testbench_busybear();
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end
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logic [31:0] InstrMask;
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logic forcedInstr;
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always @(dut.PCF) begin
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lastCheckInstrF = CheckInstrF;
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lastPC <= dut.PCF;
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lastPC2 <= lastPC;
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if (speculative && (lastPC != pcExpected)) begin
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speculative = ~equal(dut.PCF,pcExpected,3);
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end
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else begin
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if($feof(data_file_PC)) begin
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$display("no more PC data to read");
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`ERROR
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end
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scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext);
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if (PCtext != "ret" && PCtext != "fence" && PCtext != "nop" && PCtext != "mret" && PCtext != "sfence.vma" && PCtext != "unimp") begin
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scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2);
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PCtext = {PCtext, " ", PCtext2};
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end
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scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrF);
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if(CheckInstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
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CheckInstrF = 32'b0010011;
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$display("warning: NOPing out %s at PC=%0x", PCtext, dut.PCF);
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warningCount += 1;
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forcedInstr = 1;
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always @(dut.PCF or dut.hart.ifu.InstrF) begin
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if (~reset && dut.hart.ifu.InstrF !== {32{1'bx}}) begin
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lastCheckInstrF = CheckInstrF;
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lastPC <= dut.PCF;
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lastPC2 <= lastPC;
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if (speculative && (lastPC != pcExpected)) begin
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speculative = ~equal(dut.PCF,pcExpected,3);
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end
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else begin
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if(CheckInstrF[28:27] != 2'b11 && CheckInstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
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CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
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$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
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if($feof(data_file_PC)) begin
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$display("no more PC data to read");
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`ERROR
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end
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scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext);
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if (PCtext != "ret" && PCtext != "fence" && PCtext != "nop" && PCtext != "mret" && PCtext != "sfence.vma" && PCtext != "unimp") begin
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scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2);
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PCtext = {PCtext, " ", PCtext2};
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end
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scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrF);
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if(CheckInstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
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CheckInstrF = 32'b0010011;
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$display("warning: NOPing out %s at PC=%0x", PCtext, dut.PCF);
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warningCount += 1;
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forcedInstr = 1;
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end
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else begin
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forcedInstr = 0;
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if(CheckInstrF[28:27] != 2'b11 && CheckInstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
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CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
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$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
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warningCount += 1;
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forcedInstr = 1;
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end
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else begin
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forcedInstr = 0;
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end
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end
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end
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// then expected PC value
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scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
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if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) ||
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(instrs <= 1000 && instrs % 100 == 0) || (instrs <= 10000 && instrs % 1000 == 0) ||
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(instrs <= 100000 && instrs % 10000 == 0) || (instrs <= 1000000 && instrs % 100000 == 0)) begin
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$display("loaded %0d instructions", instrs);
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end
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instrs += 1;
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// are we at a branch/jump?
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casex (lastCheckInstrF[31:0])
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32'b00000000001000000000000001110011, // URET
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32'b00010000001000000000000001110011, // SRET
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32'b00110000001000000000000001110011, // MRET
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32'bXXXXXXXXXXXXXXXXXXXXXXXXX1101111, // JAL
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32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100111, // JALR
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32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100011, // B
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32'bXXXXXXXXXXXXXXXX110XXXXXXXXXXX01, // C.BEQZ
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32'bXXXXXXXXXXXXXXXX111XXXXXXXXXXX01, // C.BNEZ
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32'bXXXXXXXXXXXXXXXX101XXXXXXXXXXX01: // C.J
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speculative = 1;
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32'bXXXXXXXXXXXXXXXX1001000000000010: // C.EBREAK:
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speculative = 0; // tbh don't really know what should happen here
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32'bXXXXXXXXXXXXXXXX1000XXXXX0000010, // C.JR
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32'bXXXXXXXXXXXXXXXX1001XXXXX0000010: // C.JALR //this is RV64 only so no C.JAL
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speculative = 1;
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default:
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speculative = 0;
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endcase
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// then expected PC value
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scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
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if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) ||
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(instrs <= 1000 && instrs % 100 == 0) || (instrs <= 10000 && instrs % 1000 == 0) ||
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(instrs <= 100000 && instrs % 10000 == 0) || (instrs <= 1000000 && instrs % 100000 == 0)) begin
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$display("loaded %0d instructions", instrs);
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end
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instrs += 1;
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// are we at a branch/jump?
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casex (lastCheckInstrF[31:0])
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32'b00000000001000000000000001110011, // URET
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32'b00010000001000000000000001110011, // SRET
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32'b00110000001000000000000001110011, // MRET
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32'bXXXXXXXXXXXXXXXXXXXXXXXXX1101111, // JAL
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32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100111, // JALR
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32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100011, // B
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32'bXXXXXXXXXXXXXXXX110XXXXXXXXXXX01, // C.BEQZ
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32'bXXXXXXXXXXXXXXXX111XXXXXXXXXXX01, // C.BNEZ
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32'bXXXXXXXXXXXXXXXX101XXXXXXXXXXX01: // C.J
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speculative = 1;
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32'bXXXXXXXXXXXXXXXX1001000000000010: // C.EBREAK:
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speculative = 0; // tbh don't really know what should happen here
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32'bXXXXXXXXXXXXXXXX1000XXXXX0000010, // C.JR
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32'bXXXXXXXXXXXXXXXX1001XXXXX0000010: // C.JALR //this is RV64 only so no C.JAL
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speculative = 1;
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default:
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speculative = 0;
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endcase
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//check things!
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if ((~speculative) && (~equal(dut.PCF,pcExpected,3))) begin
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$display("%0t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, dut.PCF, pcExpected);
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`ERROR
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end
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InstrMask = CheckInstrF[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF;
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if ((~forcedInstr) && (~speculative) && ((InstrMask & dut.InstrF) !== (InstrMask & CheckInstrF))) begin
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$display("%0t ps, instr %0d: InstrF does not equal CheckInstrF: %x, %x, PC: %x", $time, instrs, dut.InstrF, CheckInstrF, dut.PCF);
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`ERROR
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//check things!
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if ((~speculative) && (~equal(dut.PCF,pcExpected,3))) begin
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$display("%0t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, dut.PCF, pcExpected);
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`ERROR
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end
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InstrMask = CheckInstrF[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF;
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if ((~forcedInstr) && (~speculative) && ((InstrMask & dut.hart.ifu.InstrF) !== (InstrMask & CheckInstrF))) begin
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$display("%0t ps, instr %0d: InstrF does not equal CheckInstrF: %x, %x, PC: %x", $time, instrs, dut.hart.ifu.InstrF, CheckInstrF, dut.PCF);
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`ERROR
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end
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end
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end
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end
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@ -440,7 +417,7 @@ module testbench_busybear();
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// Track names of instructions
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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instrNameDecTB dec(dut.InstrF, InstrFName);
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instrNameDecTB dec(dut.hart.ifu.InstrF, InstrFName);
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrM, InstrW,
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