forked from Github_Repos/cvw
Don't generate HPTW when MEM_VIRTMEM=0
This commit is contained in:
David Harris
parent
179c8d3ed4
commit
71711c54c9
@ -46,7 +46,7 @@
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`define MEM_DCACHE 0
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`define MEM_DTIM 1
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`define MEM_ICACHE 0
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`define MEM_VIRTMEM 1
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`define MEM_VIRTMEM 0\1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define ITLB_ENTRIES 32
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@ -70,484 +70,495 @@ module pagetablewalker
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output logic WalkerStorePageFaultM
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);
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// Internal signals
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// register TLBs translation miss requests
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logic [`XLEN-1:0] TranslationVAdrQ;
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logic ITLBMissFQ, DTLBMissMQ;
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logic [`PPN_BITS-1:0] BasePageTablePPN;
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logic [`XLEN-1:0] TranslationVAdr;
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logic [`XLEN-1:0] SavedPTE, CurrentPTE;
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logic [`PA_BITS-1:0] TranslationPAdr;
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logic [`PPN_BITS-1:0] CurrentPPN;
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logic [`SVMODE_BITS-1:0] SvMode;
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logic MemStore;
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// PTE Control Bits
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logic Dirty, Accessed, Global, User,
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Executable, Writable, Readable, Valid;
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// PTE descriptions
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logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE;
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// Outputs of walker
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logic [`XLEN-1:0] PageTableEntry;
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logic [1:0] PageType;
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logic StartWalk;
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logic EndWalk;
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typedef enum {LEVEL0_WDV,
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LEVEL0,
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LEVEL1_WDV,
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LEVEL1,
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LEVEL2_WDV,
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LEVEL2,
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LEVEL3_WDV,
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LEVEL3,
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LEAF,
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IDLE,
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START,
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FAULT} statetype;
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statetype WalkerState, NextWalkerState;
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logic PRegEn;
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logic SelDataTranslation;
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assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
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assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
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assign MemStore = MemRWM[0];
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// Prefer data address translations over instruction address translations
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assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; // *** need to register TranslationVAdr
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assign SelDataTranslation = DTLBMissMQ | DTLBMissM;
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flopenr #(`XLEN)
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TranslationVAdrReg(.clk(clk),
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.reset(reset),
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.en(StartWalk),
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.d(TranslationVAdr),
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.q(TranslationVAdrQ));
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flopenrc #(1)
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DTLBMissMReg(.clk(clk),
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.reset(reset),
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.en(StartWalk | EndWalk),
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.clear(EndWalk),
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.d(DTLBMissM),
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.q(DTLBMissMQ));
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flopenrc #(1)
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ITLBMissMReg(.clk(clk),
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.reset(reset),
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.en(StartWalk | EndWalk),
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.clear(EndWalk),
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.d(ITLBMissF),
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.q(ITLBMissFQ));
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assign StartWalk = WalkerState == IDLE && (DTLBMissM | ITLBMissF);
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assign EndWalk = WalkerState == LEAF ||
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//(WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) ||
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(WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) ||
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(WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) ||
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(WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) ||
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(WalkerState == FAULT);
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assign MMUTranslate = (DTLBMissMQ | ITLBMissFQ) & ~EndWalk;
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//assign MMUTranslate = DTLBMissM | ITLBMissF;
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// unswizzle PTE bits
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assign {Dirty, Accessed, Global, User,
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Executable, Writable, Readable, Valid} = CurrentPTE[7:0];
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// Assign PTE descriptors common across all XLEN values
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assign LeafPTE = Executable | Writable | Readable;
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assign ValidPTE = Valid && ~(Writable && ~Readable);
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assign AccessAlert = ~Accessed | (MemStore & ~Dirty);
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// Assign specific outputs to general outputs
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assign PageTableEntryF = PageTableEntry;
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assign PageTableEntryM = PageTableEntry;
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assign PageTypeF = PageType;
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assign PageTypeM = PageType;
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generate
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if (`XLEN == 32) begin
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logic [9:0] VPN1, VPN0;
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if (`MEM_VIRTMEM) begin
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// Internal signals
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// register TLBs translation miss requests
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logic [`XLEN-1:0] TranslationVAdrQ;
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logic ITLBMissFQ, DTLBMissMQ;
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logic [`PPN_BITS-1:0] BasePageTablePPN;
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logic [`XLEN-1:0] TranslationVAdr;
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logic [`XLEN-1:0] SavedPTE, CurrentPTE;
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logic [`PA_BITS-1:0] TranslationPAdr;
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logic [`PPN_BITS-1:0] CurrentPPN;
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logic [`SVMODE_BITS-1:0] SvMode;
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logic MemStore;
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flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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// PTE Control Bits
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logic Dirty, Accessed, Global, User,
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Executable, Writable, Readable, Valid;
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// PTE descriptions
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logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE;
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/* -----\/----- EXCLUDED -----\/-----
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assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
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-----/\----- EXCLUDED -----/\----- */
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// Outputs of walker
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logic [`XLEN-1:0] PageTableEntry;
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logic [1:0] PageType;
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logic StartWalk;
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logic EndWalk;
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typedef enum {LEVEL0_WDV,
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LEVEL0,
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LEVEL1_WDV,
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LEVEL1,
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LEVEL2_WDV,
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LEVEL2,
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LEVEL3_WDV,
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LEVEL3,
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LEAF,
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IDLE,
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START,
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FAULT} statetype;
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// State transition logic
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always_comb begin
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PRegEn = 1'b0;
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TranslationPAdr = '0;
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HPTWRead = 1'b0;
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PageTableEntry = '0;
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PageType = '0;
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DTLBWriteM = '0;
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ITLBWriteF = '0;
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WalkerInstrPageFaultF = 1'b0;
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WalkerLoadPageFaultM = 1'b0;
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WalkerStorePageFaultM = 1'b0;
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statetype WalkerState, NextWalkerState;
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case (WalkerState)
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IDLE: begin
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if (MMUTranslate && SvMode == `SV32) begin // *** Added SvMode
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NextWalkerState = START;
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end else begin
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NextWalkerState = IDLE;
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end
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end
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logic PRegEn;
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logic SelDataTranslation;
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assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
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START: begin
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NextWalkerState = LEVEL1_WDV;
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TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
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HPTWRead = 1'b1;
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end
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LEVEL1_WDV: begin
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TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
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if (HPTWStall) begin
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NextWalkerState = LEVEL1_WDV;
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end else begin
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NextWalkerState = LEVEL1;
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PRegEn = 1'b1;
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end
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end
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LEVEL1: begin
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// *** <FUTURE WORK> According to the architecture, we should
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// fault upon finding a superpage that is misaligned or has 0
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// access bit. The following commented line of code is
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// supposed to perform that check. However, it is untested.
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if (ValidPTE && LeafPTE && ~BadMegapage) begin
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NextWalkerState = LEAF;
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PageTableEntry = CurrentPTE;
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PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux?
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DTLBWriteM = DTLBMissMQ;
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ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
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TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]};
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end
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
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else if (ValidPTE && ~LeafPTE) begin
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NextWalkerState = LEVEL0_WDV;
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TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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HPTWRead = 1'b1;
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end else begin
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NextWalkerState = FAULT;
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end
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end
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LEVEL0_WDV: begin
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TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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if (HPTWStall) begin
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NextWalkerState = LEVEL0_WDV;
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end else begin
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NextWalkerState = LEVEL0;
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PRegEn = 1'b1;
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end
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end
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assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
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LEVEL0: begin
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if (ValidPTE & LeafPTE & ~AccessAlert) begin
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NextWalkerState = LEAF;
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PageTableEntry = CurrentPTE;
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PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00;
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DTLBWriteM = DTLBMissMQ;
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ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
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TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]};
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end else begin
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NextWalkerState = FAULT;
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end
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end
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LEAF: begin
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NextWalkerState = IDLE;
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end
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FAULT: begin
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NextWalkerState = IDLE;
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WalkerInstrPageFaultF = ~DTLBMissMQ;
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WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
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WalkerStorePageFaultM = DTLBMissMQ && MemStore;
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end
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// Default case should never happen, but is included for linter.
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default: NextWalkerState = IDLE;
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endcase
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end
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assign MemStore = MemRWM[0];
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// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
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assign MegapageMisaligned = |(CurrentPPN[9:0]);
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assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
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// Prefer data address translations over instruction address translations
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assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; // *** need to register TranslationVAdr
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assign SelDataTranslation = DTLBMissMQ | DTLBMissM;
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assign VPN1 = TranslationVAdrQ[31:22];
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assign VPN0 = TranslationVAdrQ[21:12];
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flopenr #(`XLEN)
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TranslationVAdrReg(.clk(clk),
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.reset(reset),
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.en(StartWalk),
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.d(TranslationVAdr),
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.q(TranslationVAdrQ));
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flopenrc #(1)
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DTLBMissMReg(.clk(clk),
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.reset(reset),
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.en(StartWalk | EndWalk),
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.clear(EndWalk),
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.d(DTLBMissM),
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.q(DTLBMissMQ));
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flopenrc #(1)
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ITLBMissMReg(.clk(clk),
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.reset(reset),
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.en(StartWalk | EndWalk),
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.clear(EndWalk),
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.d(ITLBMissF),
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.q(ITLBMissFQ));
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// Capture page table entry from data cache
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// *** may need to delay reading this value until the next clock cycle.
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// The clk to q latency of the SRAM in the data cache will be long.
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// I cannot see directly using this value. This is no different than
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// a load delay hazard. This will require rewriting the walker fsm.
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// also need a new signal to save. Should be a mealy output of the fsm
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// request followed by ~stall.
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flopenr #(32) ptereg(clk, reset, PRegEn, MMUReadPTE, SavedPTE);
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//mux2 #(32) ptemux(SavedPTE, MMUReadPTE, PRegEn, CurrentPTE);
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assign CurrentPTE = SavedPTE;
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assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
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// Assign outputs to ahblite
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// *** Currently truncate address to 32 bits. This must be changed if
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// we support larger physical address spaces
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assign MMUPAdr = TranslationPAdr[31:0];
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end else begin
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assign StartWalk = WalkerState == IDLE && (DTLBMissM | ITLBMissF);
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assign EndWalk = WalkerState == LEAF ||
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//(WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) ||
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(WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) ||
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(WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) ||
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(WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) ||
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(WalkerState == FAULT);
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logic [8:0] VPN3, VPN2, VPN1, VPN0;
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assign MMUTranslate = (DTLBMissMQ | ITLBMissFQ) & ~EndWalk;
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//assign MMUTranslate = DTLBMissM | ITLBMissF;
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logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage;
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// unswizzle PTE bits
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assign {Dirty, Accessed, Global, User,
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Executable, Writable, Readable, Valid} = CurrentPTE[7:0];
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flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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// Assign PTE descriptors common across all XLEN values
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assign LeafPTE = Executable | Writable | Readable;
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assign ValidPTE = Valid && ~(Writable && ~Readable);
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assign AccessAlert = ~Accessed | (MemStore & ~Dirty);
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/* -----\/----- EXCLUDED -----\/-----
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assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV ||
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WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall;
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-----/\----- EXCLUDED -----/\----- */
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// Assign specific outputs to general outputs
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assign PageTableEntryF = PageTableEntry;
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assign PageTableEntryM = PageTableEntry;
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assign PageTypeF = PageType;
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assign PageTypeM = PageType;
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//assign HPTWRead = (WalkerState == IDLE && MMUTranslate) || WalkerState == LEVEL3 ||
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// WalkerState == LEVEL2 || WalkerState == LEVEL1;
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// generate
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if (`XLEN == 32) begin
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logic [9:0] VPN1, VPN0;
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flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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/* -----\/----- EXCLUDED -----\/-----
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assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
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-----/\----- EXCLUDED -----/\----- */
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// State transition logic
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always_comb begin
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PRegEn = 1'b0;
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TranslationPAdr = '0;
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HPTWRead = 1'b0;
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PageTableEntry = '0;
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PageType = '0;
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DTLBWriteM = '0;
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ITLBWriteF = '0;
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WalkerInstrPageFaultF = 1'b0;
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WalkerLoadPageFaultM = 1'b0;
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WalkerStorePageFaultM = 1'b0;
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always_comb begin
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PRegEn = 1'b0;
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TranslationPAdr = '0;
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HPTWRead = 1'b0;
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PageTableEntry = '0;
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PageType = '0;
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DTLBWriteM = '0;
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ITLBWriteF = '0;
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WalkerInstrPageFaultF = 1'b0;
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WalkerLoadPageFaultM = 1'b0;
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WalkerStorePageFaultM = 1'b0;
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case (WalkerState)
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IDLE: begin
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if (MMUTranslate && SvMode == `SV32) begin // *** Added SvMode
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NextWalkerState = START;
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end else begin
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NextWalkerState = IDLE;
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end
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end
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case (WalkerState)
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IDLE: begin
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if (MMUTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin
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NextWalkerState = START;
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end else begin
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NextWalkerState = IDLE;
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end
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end
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START: begin
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if (MMUTranslate && SvMode == `SV48) begin
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NextWalkerState = LEVEL3_WDV;
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TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
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HPTWRead = 1'b1;
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end else if (MMUTranslate && SvMode == `SV39) begin
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NextWalkerState = LEVEL2_WDV;
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TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000};
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HPTWRead = 1'b1;
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end else begin // *** should not get here
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NextWalkerState = IDLE;
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TranslationPAdr = '0;
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end
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end
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LEVEL3_WDV: begin
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TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
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if (HPTWStall) begin
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NextWalkerState = LEVEL3_WDV;
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end else begin
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NextWalkerState = LEVEL3;
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PRegEn = 1'b1;
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end
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end
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LEVEL3: begin
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// *** <FUTURE WORK> According to the architecture, we should
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// fault upon finding a superpage that is misaligned or has 0
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// access bit. The following commented line of code is
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// supposed to perform that check. However, it is untested.
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if (ValidPTE && LeafPTE && ~BadTerapage) begin
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NextWalkerState = LEAF;
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PageTableEntry = CurrentPTE;
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PageType = (WalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux?
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((WalkerState == LEVEL2) ? 2'b10 :
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((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
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DTLBWriteM = DTLBMissMQ;
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ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
|
||||
end
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||
else if (ValidPTE && ~LeafPTE) begin
|
||||
NextWalkerState = LEVEL2_WDV;
|
||||
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
|
||||
HPTWRead = 1'b1;
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
end
|
||||
START: begin
|
||||
NextWalkerState = LEVEL1_WDV;
|
||||
TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
|
||||
HPTWRead = 1'b1;
|
||||
end
|
||||
|
||||
LEVEL1_WDV: begin
|
||||
TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
|
||||
if (HPTWStall) begin
|
||||
NextWalkerState = LEVEL1_WDV;
|
||||
end else begin
|
||||
NextWalkerState = LEVEL1;
|
||||
PRegEn = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
LEVEL1: begin
|
||||
// *** <FUTURE WORK> According to the architecture, we should
|
||||
// fault upon finding a superpage that is misaligned or has 0
|
||||
// access bit. The following commented line of code is
|
||||
// supposed to perform that check. However, it is untested.
|
||||
if (ValidPTE && LeafPTE && ~BadMegapage) begin
|
||||
NextWalkerState = LEAF;
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux?
|
||||
DTLBWriteM = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]};
|
||||
end
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||
else if (ValidPTE && ~LeafPTE) begin
|
||||
NextWalkerState = LEVEL0_WDV;
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
|
||||
HPTWRead = 1'b1;
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
end
|
||||
end
|
||||
|
||||
LEVEL0_WDV: begin
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
|
||||
if (HPTWStall) begin
|
||||
NextWalkerState = LEVEL0_WDV;
|
||||
end else begin
|
||||
NextWalkerState = LEVEL0;
|
||||
PRegEn = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
LEVEL0: begin
|
||||
if (ValidPTE & LeafPTE & ~AccessAlert) begin
|
||||
NextWalkerState = LEAF;
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00;
|
||||
DTLBWriteM = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]};
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
end
|
||||
end
|
||||
|
||||
LEAF: begin
|
||||
NextWalkerState = IDLE;
|
||||
end
|
||||
FAULT: begin
|
||||
NextWalkerState = IDLE;
|
||||
WalkerInstrPageFaultF = ~DTLBMissMQ;
|
||||
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
|
||||
WalkerStorePageFaultM = DTLBMissMQ && MemStore;
|
||||
end
|
||||
|
||||
// Default case should never happen, but is included for linter.
|
||||
default: NextWalkerState = IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
LEVEL2_WDV: begin
|
||||
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
|
||||
//HPTWRead = 1'b1;
|
||||
if (HPTWStall) begin
|
||||
NextWalkerState = LEVEL2_WDV;
|
||||
end else begin
|
||||
NextWalkerState = LEVEL2;
|
||||
PRegEn = 1'b1;
|
||||
end
|
||||
end
|
||||
// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
|
||||
assign MegapageMisaligned = |(CurrentPPN[9:0]);
|
||||
assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
||||
|
||||
assign VPN1 = TranslationVAdrQ[31:22];
|
||||
assign VPN0 = TranslationVAdrQ[21:12];
|
||||
|
||||
|
||||
LEVEL2: begin
|
||||
// *** <FUTURE WORK> According to the architecture, we should
|
||||
// fault upon finding a superpage that is misaligned or has 0
|
||||
// access bit. The following commented line of code is
|
||||
// supposed to perform that check. However, it is untested.
|
||||
if (ValidPTE && LeafPTE && ~BadGigapage) begin
|
||||
NextWalkerState = LEAF;
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (WalkerState == LEVEL3) ? 2'b11 :
|
||||
((WalkerState == LEVEL2) ? 2'b10 :
|
||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||
DTLBWriteM = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
|
||||
end
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||
else if (ValidPTE && ~LeafPTE) begin
|
||||
NextWalkerState = LEVEL1_WDV;
|
||||
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
||||
HPTWRead = 1'b1;
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
end
|
||||
|
||||
// Capture page table entry from data cache
|
||||
// *** may need to delay reading this value until the next clock cycle.
|
||||
// The clk to q latency of the SRAM in the data cache will be long.
|
||||
// I cannot see directly using this value. This is no different than
|
||||
// a load delay hazard. This will require rewriting the walker fsm.
|
||||
// also need a new signal to save. Should be a mealy output of the fsm
|
||||
// request followed by ~stall.
|
||||
flopenr #(32) ptereg(clk, reset, PRegEn, MMUReadPTE, SavedPTE);
|
||||
//mux2 #(32) ptemux(SavedPTE, MMUReadPTE, PRegEn, CurrentPTE);
|
||||
assign CurrentPTE = SavedPTE;
|
||||
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
|
||||
|
||||
// Assign outputs to ahblite
|
||||
// *** Currently truncate address to 32 bits. This must be changed if
|
||||
// we support larger physical address spaces
|
||||
assign MMUPAdr = TranslationPAdr[31:0];
|
||||
|
||||
end else begin
|
||||
|
||||
logic [8:0] VPN3, VPN2, VPN1, VPN0;
|
||||
|
||||
logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage;
|
||||
|
||||
flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
|
||||
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV ||
|
||||
WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall;
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
//assign HPTWRead = (WalkerState == IDLE && MMUTranslate) || WalkerState == LEVEL3 ||
|
||||
// WalkerState == LEVEL2 || WalkerState == LEVEL1;
|
||||
|
||||
|
||||
always_comb begin
|
||||
PRegEn = 1'b0;
|
||||
TranslationPAdr = '0;
|
||||
HPTWRead = 1'b0;
|
||||
PageTableEntry = '0;
|
||||
PageType = '0;
|
||||
DTLBWriteM = '0;
|
||||
ITLBWriteF = '0;
|
||||
|
||||
WalkerInstrPageFaultF = 1'b0;
|
||||
WalkerLoadPageFaultM = 1'b0;
|
||||
WalkerStorePageFaultM = 1'b0;
|
||||
|
||||
case (WalkerState)
|
||||
IDLE: begin
|
||||
if (MMUTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin
|
||||
NextWalkerState = START;
|
||||
end else begin
|
||||
NextWalkerState = IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
LEVEL1_WDV: begin
|
||||
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
||||
//HPTWRead = 1'b1;
|
||||
if (HPTWStall) begin
|
||||
NextWalkerState = LEVEL1_WDV;
|
||||
end else begin
|
||||
NextWalkerState = LEVEL1;
|
||||
PRegEn = 1'b1;
|
||||
end
|
||||
START: begin
|
||||
if (MMUTranslate && SvMode == `SV48) begin
|
||||
NextWalkerState = LEVEL3_WDV;
|
||||
TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
|
||||
HPTWRead = 1'b1;
|
||||
end else if (MMUTranslate && SvMode == `SV39) begin
|
||||
NextWalkerState = LEVEL2_WDV;
|
||||
TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000};
|
||||
HPTWRead = 1'b1;
|
||||
end else begin // *** should not get here
|
||||
NextWalkerState = IDLE;
|
||||
TranslationPAdr = '0;
|
||||
end
|
||||
end
|
||||
|
||||
LEVEL1: begin
|
||||
// *** <FUTURE WORK> According to the architecture, we should
|
||||
// fault upon finding a superpage that is misaligned or has 0
|
||||
// access bit. The following commented line of code is
|
||||
// supposed to perform that check. However, it is untested.
|
||||
if (ValidPTE && LeafPTE && ~BadMegapage) begin
|
||||
NextWalkerState = LEAF;
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (WalkerState == LEVEL3) ? 2'b11 :
|
||||
((WalkerState == LEVEL2) ? 2'b10 :
|
||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||
DTLBWriteM = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
|
||||
LEVEL3_WDV: begin
|
||||
TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
|
||||
if (HPTWStall) begin
|
||||
NextWalkerState = LEVEL3_WDV;
|
||||
end else begin
|
||||
NextWalkerState = LEVEL3;
|
||||
PRegEn = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
LEVEL3: begin
|
||||
// *** <FUTURE WORK> According to the architecture, we should
|
||||
// fault upon finding a superpage that is misaligned or has 0
|
||||
// access bit. The following commented line of code is
|
||||
// supposed to perform that check. However, it is untested.
|
||||
if (ValidPTE && LeafPTE && ~BadTerapage) begin
|
||||
NextWalkerState = LEAF;
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (WalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux?
|
||||
((WalkerState == LEVEL2) ? 2'b10 :
|
||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||
DTLBWriteM = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
|
||||
end
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||
else if (ValidPTE && ~LeafPTE) begin
|
||||
NextWalkerState = LEVEL2_WDV;
|
||||
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
|
||||
HPTWRead = 1'b1;
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
LEVEL2_WDV: begin
|
||||
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
|
||||
//HPTWRead = 1'b1;
|
||||
if (HPTWStall) begin
|
||||
NextWalkerState = LEVEL2_WDV;
|
||||
end else begin
|
||||
NextWalkerState = LEVEL2;
|
||||
PRegEn = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||
else if (ValidPTE && ~LeafPTE) begin
|
||||
NextWalkerState = LEVEL0_WDV;
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
HPTWRead = 1'b1;
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
end
|
||||
LEVEL2: begin
|
||||
// *** <FUTURE WORK> According to the architecture, we should
|
||||
// fault upon finding a superpage that is misaligned or has 0
|
||||
// access bit. The following commented line of code is
|
||||
// supposed to perform that check. However, it is untested.
|
||||
if (ValidPTE && LeafPTE && ~BadGigapage) begin
|
||||
NextWalkerState = LEAF;
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (WalkerState == LEVEL3) ? 2'b11 :
|
||||
((WalkerState == LEVEL2) ? 2'b10 :
|
||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||
DTLBWriteM = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
|
||||
end
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||
else if (ValidPTE && ~LeafPTE) begin
|
||||
NextWalkerState = LEVEL1_WDV;
|
||||
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
||||
HPTWRead = 1'b1;
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
LEVEL1_WDV: begin
|
||||
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
||||
//HPTWRead = 1'b1;
|
||||
if (HPTWStall) begin
|
||||
NextWalkerState = LEVEL1_WDV;
|
||||
end else begin
|
||||
NextWalkerState = LEVEL1;
|
||||
PRegEn = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
LEVEL1: begin
|
||||
// *** <FUTURE WORK> According to the architecture, we should
|
||||
// fault upon finding a superpage that is misaligned or has 0
|
||||
// access bit. The following commented line of code is
|
||||
// supposed to perform that check. However, it is untested.
|
||||
if (ValidPTE && LeafPTE && ~BadMegapage) begin
|
||||
NextWalkerState = LEAF;
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (WalkerState == LEVEL3) ? 2'b11 :
|
||||
((WalkerState == LEVEL2) ? 2'b10 :
|
||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||
DTLBWriteM = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
|
||||
|
||||
end
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||
else if (ValidPTE && ~LeafPTE) begin
|
||||
NextWalkerState = LEVEL0_WDV;
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
HPTWRead = 1'b1;
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
end
|
||||
end
|
||||
|
||||
LEVEL0_WDV: begin
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
if (HPTWStall) begin
|
||||
NextWalkerState = LEVEL0_WDV;
|
||||
end else begin
|
||||
NextWalkerState = LEVEL0;
|
||||
PRegEn = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
LEVEL0: begin
|
||||
if (ValidPTE && LeafPTE && ~AccessAlert) begin
|
||||
NextWalkerState = LEAF;
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (WalkerState == LEVEL3) ? 2'b11 :
|
||||
((WalkerState == LEVEL2) ? 2'b10 :
|
||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||
DTLBWriteM = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
end
|
||||
end
|
||||
|
||||
LEAF: begin
|
||||
NextWalkerState = IDLE;
|
||||
end
|
||||
|
||||
FAULT: begin
|
||||
NextWalkerState = IDLE;
|
||||
WalkerInstrPageFaultF = ~DTLBMissMQ;
|
||||
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
|
||||
WalkerStorePageFaultM = DTLBMissMQ && MemStore;
|
||||
end
|
||||
|
||||
// Default case should never happen
|
||||
default: begin
|
||||
NextWalkerState = IDLE;
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
LEVEL0_WDV: begin
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
if (HPTWStall) begin
|
||||
NextWalkerState = LEVEL0_WDV;
|
||||
end else begin
|
||||
NextWalkerState = LEVEL0;
|
||||
PRegEn = 1'b1;
|
||||
end
|
||||
end
|
||||
// A terapage is a level 3 leaf page. This page must have zero PPN[2],
|
||||
// zero PPN[1], and zero PPN[0]
|
||||
assign TerapageMisaligned = |(CurrentPPN[26:0]);
|
||||
// A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and
|
||||
// zero PPN[0]
|
||||
assign GigapageMisaligned = |(CurrentPPN[17:0]);
|
||||
// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
|
||||
assign MegapageMisaligned = |(CurrentPPN[8:0]);
|
||||
|
||||
LEVEL0: begin
|
||||
if (ValidPTE && LeafPTE && ~AccessAlert) begin
|
||||
NextWalkerState = LEAF;
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (WalkerState == LEVEL3) ? 2'b11 :
|
||||
((WalkerState == LEVEL2) ? 2'b10 :
|
||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||
DTLBWriteM = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
end
|
||||
end
|
||||
|
||||
LEAF: begin
|
||||
NextWalkerState = IDLE;
|
||||
end
|
||||
assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
||||
assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
||||
assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
||||
|
||||
FAULT: begin
|
||||
NextWalkerState = IDLE;
|
||||
WalkerInstrPageFaultF = ~DTLBMissMQ;
|
||||
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
|
||||
WalkerStorePageFaultM = DTLBMissMQ && MemStore;
|
||||
end
|
||||
|
||||
// Default case should never happen
|
||||
default: begin
|
||||
NextWalkerState = IDLE;
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
// A terapage is a level 3 leaf page. This page must have zero PPN[2],
|
||||
// zero PPN[1], and zero PPN[0]
|
||||
assign TerapageMisaligned = |(CurrentPPN[26:0]);
|
||||
// A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and
|
||||
// zero PPN[0]
|
||||
assign GigapageMisaligned = |(CurrentPPN[17:0]);
|
||||
// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
|
||||
assign MegapageMisaligned = |(CurrentPPN[8:0]);
|
||||
|
||||
assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
||||
assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
||||
assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
||||
|
||||
assign VPN3 = TranslationVAdrQ[47:39];
|
||||
assign VPN2 = TranslationVAdrQ[38:30];
|
||||
assign VPN1 = TranslationVAdrQ[29:21];
|
||||
assign VPN0 = TranslationVAdrQ[20:12];
|
||||
assign VPN3 = TranslationVAdrQ[47:39];
|
||||
assign VPN2 = TranslationVAdrQ[38:30];
|
||||
assign VPN1 = TranslationVAdrQ[29:21];
|
||||
assign VPN0 = TranslationVAdrQ[20:12];
|
||||
|
||||
|
||||
// Capture page table entry from ahblite
|
||||
flopenr #(`XLEN) ptereg(clk, reset, PRegEn, MMUReadPTE, SavedPTE);
|
||||
//mux2 #(`XLEN) ptemux(SavedPTE, MMUReadPTE, PRegEn, CurrentPTE);
|
||||
assign CurrentPTE = SavedPTE;
|
||||
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
|
||||
// Capture page table entry from ahblite
|
||||
flopenr #(`XLEN) ptereg(clk, reset, PRegEn, MMUReadPTE, SavedPTE);
|
||||
//mux2 #(`XLEN) ptemux(SavedPTE, MMUReadPTE, PRegEn, CurrentPTE);
|
||||
assign CurrentPTE = SavedPTE;
|
||||
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
|
||||
|
||||
// Assign outputs to ahblite
|
||||
// *** Currently truncate address to 32 bits. This must be changed if
|
||||
// we support larger physical address spaces
|
||||
assign MMUPAdr = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
|
||||
// Assign outputs to ahblite
|
||||
// *** Currently truncate address to 32 bits. This must be changed if
|
||||
// we support larger physical address spaces
|
||||
assign MMUPAdr = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
|
||||
end
|
||||
//endgenerate
|
||||
end else begin
|
||||
assign MMUPAdr = 0;
|
||||
assign MMUTranslate = 0;
|
||||
assign HPTWRead = 0;
|
||||
assign WalkerInstrPageFaultF = 0;
|
||||
assign WalkerLoadPageFaultM = 0;
|
||||
assign WalkerStorePageFaultM = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user