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Merge remote-tracking branch 'origin/fixPrivTests' into main

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This commit is contained in:
bbracker 2021-06-15 09:57:46 -04:00
commit cd00e04943
7 changed files with 61 additions and 41 deletions
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66
wally-pipelined/src/uncore/clint.sv
View File

@ -27,23 +27,30 @@
`include "wally-config.vh"
module clint (
input logic HCLK, HRESETn,
input logic HSELCLINT,
input logic [15:0] HADDR,
input logic HWRITE,
input logic [`XLEN-1:0] HWDATA,
input logic HCLK, HRESETn,
input logic HSELCLINT,
input logic [15:0] HADDR,
input logic HWRITE,
input logic [`XLEN-1:0] HWDATA,
output logic [`XLEN-1:0] HREADCLINT,
output logic HRESPCLINT, HREADYCLINT,
output logic TimerIntM, SwIntM);
output logic HRESPCLINT, HREADYCLINT,
input logic HREADY,
input logic [1:0] HTRANS,
output logic TimerIntM, SwIntM);
logic [63:0] MTIMECMP, MTIME;
logic MSIP;
logic [15:0] entry;
logic [15:0] entry, entryd;
logic memread, memwrite;
logic initTrans;
assign initTrans = HREADY & HSELCLINT & (HTRANS != 2'b00);
assign memread = initTrans & ~HWRITE;
// entryd and memwrite are delayed by a cycle because AHB controller waits a cycle before outputting write data
flopr #(1) memwriteflop(HCLK, ~HRESETn, initTrans & HWRITE, memwrite);
flopr #(16) entrydflop(HCLK, ~HRESETn, entry, entryd);
assign memread = HSELCLINT & ~HWRITE;
assign memwrite = HSELCLINT & HWRITE;
assign HRESPCLINT = 0; // OK
assign HREADYCLINT = 1'b1; // will need to be modified if CLINT ever needs more than 1 cycle to do something
@ -75,16 +82,22 @@ module clint (
always_ff @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
MSIP <= 0;
MTIME <= 0;
MTIMECMP <= 0;
// MTIMECMP is not reset
end else if (memwrite) begin
if (entry == 16'h0000) MSIP <= HWDATA[0];
if (entry == 16'h4000) MTIMECMP <= HWDATA;
if (entryd == 16'h0000) MSIP <= HWDATA[0];
if (entryd == 16'h4000) MTIMECMP <= HWDATA;
// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
if (entry == 16'hBFF8) MTIME <= HWDATA;
else MTIME <= MTIME + 1;
end
always_ff @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
MTIME <= 0;
// MTIMECMP is not reset
end else if (memwrite && entryd == 16'hBFF8) begin
// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
MTIME <= HWDATA;
end else MTIME <= MTIME + 1;
end else begin // 32-bit
always @(posedge HCLK) begin
case(entry)
@ -99,18 +112,25 @@ module clint (
always_ff @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
MSIP <= 0;
MTIME <= 0;
MTIMECMP <= 0;
// MTIMECMP is not reset
end else if (memwrite) begin
if (entry == 16'h0000) MSIP <= HWDATA[0];
if (entry == 16'h4000) MTIMECMP[31:0] <= HWDATA;
if (entry == 16'h4004) MTIMECMP[63:32] <= HWDATA;
if (entryd == 16'h0000) MSIP <= HWDATA[0];
if (entryd == 16'h4000) MTIMECMP[31:0] <= HWDATA;
if (entryd == 16'h4004) MTIMECMP[63:32] <= HWDATA;
// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
if (entry == 16'hBFF8) MTIME[31:0] <= HWDATA;
else if (entry == 16'hBFFC) MTIME[63:32]<= HWDATA;
else MTIME <= MTIME + 1;
end
end
always_ff @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
MTIME <= 0;
// MTIMECMP is not reset
end else if (memwrite && (entryd == 16'hBFF8)) begin
MTIME[31:0] <= HWDATA;
end else if (memwrite && (entryd == 16'hBFFC)) begin
// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
MTIME[63:32]<= HWDATA;
end else MTIME <= MTIME + 1;
end
endgenerate

8
wally-pipelined/testgen/privileged/testgen-CAUSE.py
View File

@ -503,9 +503,9 @@ for xlen in xlens:
if fromMode == "s" or fromMode == "u":
lines += f"""
li x1, 0b110000000000
csrrc x28, mstatus, x1
csrrc x31, mstatus, x1
li x1, 0b0100000000000
csrrs x28, mstatus, x1
csrrs x31, mstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction
@ -520,7 +520,7 @@ for xlen in xlens:
lines += f"""
li x1, 0b110000000000
csrrc x28, sstatus, x1
csrrc x31, sstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the sret instruction
@ -567,4 +567,4 @@ for xlen in xlens:
lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
f.write(lines)
f.close()
r.close()
r.close()

4
wally-pipelined/testgen/privileged/testgen-DELEG.py
View File

@ -233,9 +233,9 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
{beforeTest}
li x1, 0b110000000000
csrrc x28, {testMode}status, x1
csrrc x31, {testMode}status, x1
li x1, 0b{"01" if mode == "s" else "00"}00000000000
csrrs x28, {testMode}status, x1
csrrs x31, {testMode}status, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the ret instruction

8
wally-pipelined/testgen/privileged/testgen-EPC.py
View File

@ -210,9 +210,9 @@ for xlen in xlens:
if fromMode == "s" or fromMode == "u":
lines += f"""
li x1, 0b110000000000
csrrc x28, mstatus, x1
csrrc x31, mstatus, x1
li x1, 0b0100000000000
csrrs x28, mstatus, x1
csrrs x31, mstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction
@ -226,7 +226,7 @@ for xlen in xlens:
lines += f"""
li x1, 0b110000000000
csrrc x28, sstatus, x1
csrrc x31, sstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the sret instruction
@ -260,4 +260,4 @@ for xlen in xlens:
lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
f.write(lines)
f.close()
r.close()
r.close()

4
wally-pipelined/testgen/privileged/testgen-IE.py
View File

@ -346,9 +346,9 @@ for xlen in xlens:
# bring down to supervisor mode
lines += f"""
li x1, 0b110000000000
csrrc x28, mstatus, x1
csrrc x31, mstatus, x1
li x1, 0b0100000000000
csrrs x28, mstatus, x1
csrrs x31, mstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction

6
wally-pipelined/testgen/privileged/testgen-TVAL.py
View File

@ -304,9 +304,9 @@ for xlen in xlens:
if fromMode == "s" or fromMode == "u":
lines += f"""
li x1, 0b110000000000
csrrc x28, mstatus, x1
csrrc x31, mstatus, x1
li x1, 0b0100000000000
csrrs x28, mstatus, x1
csrrs x31, mstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction
@ -321,7 +321,7 @@ for xlen in xlens:
lines += f"""
li x1, 0b110000000000
csrrc x28, sstatus, x1
csrrc x31, sstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the sret instruction

6
wally-pipelined/testgen/privileged/testgen-TVEC.py
View File

@ -406,9 +406,9 @@ for xlen in xlens:
if fromMode == "s" or fromMode == "u":
lines += f"""
li x1, 0b110000000000
csrrc x28, mstatus, x1
csrrc x31, mstatus, x1
li x1, 0b0100000000000
csrrs x28, mstatus, x1
csrrs x31, mstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction
@ -423,7 +423,7 @@ for xlen in xlens:
lines += f"""
li x1, 0b110000000000
csrrc x28, sstatus, x1
csrrc x31, sstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the sret instruction