forked from Github_Repos/cvw
busybear: instantiate soc instead of hart
This commit is contained in:
Noah Boorstin
parent
62d9185212
commit
ceb7df3561
@ -42,84 +42,84 @@ add wave /testbench_busybear/reset
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add wave -divider
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add wave -hex /testbench_busybear/PCtext
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add wave -hex /testbench_busybear/pcExpected
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add wave -hex /testbench_busybear/dut/ifu/PCF
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add wave -hex /testbench_busybear/dut/ifu/InstrF
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add wave -hex /testbench_busybear/dut/hart/ifu/PCF
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add wave -hex /testbench_busybear/dut/hart/ifu/InstrF
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add wave /testbench_busybear/lastInstrF
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add wave /testbench_busybear/speculative
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add wave /testbench_busybear/lastPC2
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add wave -divider
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#add wave -hex /testbench_busybear/dut/priv/csr/MTVEC_REG
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#add wave -hex /testbench_busybear/dut/priv/csr/MSTATUS_REG
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#add wave -hex /testbench_busybear/dut/priv/csr/SCOUNTEREN_REG
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#add wave -hex /testbench_busybear/dut/priv/csr/MIE_REG
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#add wave -hex /testbench_busybear/dut/priv/csr/MIDELEG_REG
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#add wave -hex /testbench_busybear/dut/priv/csr/MEDELEG_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIE_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIDELEG_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MEDELEG_REG
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add wave -divider
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# registers!
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add wave -hex /testbench_busybear/regExpected
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add wave -hex /testbench_busybear/regNumExpected
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add wave -hex /testbench_busybear/HWRITE
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add wave -hex /testbench_busybear/dut/MemRWM[1]
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add wave -hex /testbench_busybear/dut/hart/MemRWM[1]
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add wave -hex /testbench_busybear/HWDATA
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add wave -hex /testbench_busybear/HRDATA
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add wave -hex /testbench_busybear/HADDR
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[1]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[2]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[3]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[4]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[5]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[6]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[7]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[8]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[9]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[10]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[11]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[12]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[13]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[14]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[15]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[16]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[17]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[18]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[19]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[20]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[21]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[22]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[23]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[24]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[25]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[26]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[27]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[28]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[29]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[30]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[31]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[1]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[2]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[3]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[4]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[5]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[6]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[7]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[8]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[9]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[10]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[11]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[12]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[13]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[14]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[15]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[16]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[17]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[18]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[19]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[20]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[21]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[22]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[23]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[24]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[25]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[26]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[27]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[28]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[29]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[30]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[31]
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add wave /testbench_busybear/InstrFName
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add wave -hex /testbench_busybear/dut/ifu/PCD
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#add wave -hex /testbench_busybear/dut/ifu/InstrD
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add wave -hex /testbench_busybear/dut/hart/ifu/PCD
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#add wave -hex /testbench_busybear/dut/hart/ifu/InstrD
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add wave /testbench_busybear/InstrDName
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#add wave -divider
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add wave -hex /testbench_busybear/dut/ifu/PCE
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##add wave -hex /testbench_busybear/dut/ifu/InstrE
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add wave -hex /testbench_busybear/dut/hart/ifu/PCE
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##add wave -hex /testbench_busybear/dut/hart/ifu/InstrE
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add wave /testbench_busybear/InstrEName
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#add wave -hex /testbench_busybear/dut/ieu/dp/SrcAE
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#add wave -hex /testbench_busybear/dut/ieu/dp/SrcBE
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add wave -hex /testbench_busybear/dut/ieu/dp/ALUResultE
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#add wave /testbench_busybear/dut/ieu/dp/PCSrcE
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#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcAE
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#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcBE
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/ALUResultE
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#add wave /testbench_busybear/dut/hart/ieu/dp/PCSrcE
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#add wave -divider
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add wave -hex /testbench_busybear/dut/ifu/PCM
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##add wave -hex /testbench_busybear/dut/ifu/InstrM
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add wave -hex /testbench_busybear/dut/hart/ifu/PCM
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##add wave -hex /testbench_busybear/dut/hart/ifu/InstrM
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add wave /testbench_busybear/InstrMName
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#add wave /testbench_busybear/dut/dmem/dtim/memwrite
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#add wave -hex /testbench_busybear/dut/dmem/AdrM
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#add wave -hex /testbench_busybear/dut/dmem/WriteDataM
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#add wave /testbench_busybear/dut/hart/dmem/dtim/memwrite
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#add wave -hex /testbench_busybear/dut/hart/dmem/AdrM
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#add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM
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#add wave -divider
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add wave -hex /testbench_busybear/dut/ifu/PCW
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##add wave -hex /testbench_busybear/dut/ifu/InstrW
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add wave -hex /testbench_busybear/dut/hart/ifu/PCW
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##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW
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add wave /testbench_busybear/InstrWName
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#add wave /testbench_busybear/dut/ieu/dp/RegWriteW
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#add wave -hex /testbench_busybear/dut/ieu/dp/ResultW
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#add wave -hex /testbench_busybear/dut/ieu/dp/RdW
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#add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW
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#add wave -hex /testbench_busybear/dut/hart/ieu/dp/ResultW
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#add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW
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#add wave -divider
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##add ww
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#add wave -hex -r /testbench_busybear/*
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81
wally-pipelined/src/wally/wallypipelinedsocbusybear.sv
Normal file
81
wally-pipelined/src/wally/wallypipelinedsocbusybear.sv
Normal file
@ -0,0 +1,81 @@
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///////////////////////////////////////////
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// wally-pipelinedsoc.sv
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//
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// Written: David_Harris@hmc.edu 6 November 2020
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// Modified:
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//
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// Purpose: System on chip including pipelined processor and memories
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// Full RV32/64IC instruction set
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//
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// Note: the CSRs do not support the following features
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//- Disabling portions of the instruction set with bits of the MISA register
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//- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register
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// As of January 2020, virtual memory is not yet supported
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module wallypipelinedsocbusybear (
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input logic clk, reset,
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// AHB Lite Interface
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// inputs from external memory
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input logic [`AHBW-1:0] HRDATAEXT,
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input logic HREADYEXT, HRESPEXT,
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// outputs to external memory, shared with uncore memory
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output logic HCLK, HRESETn,
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output logic [31:0] HADDR,
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output logic [`AHBW-1:0] HWDATA,
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output logic HWRITE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK,
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// I/O Interface
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input logic [31:0] GPIOPinsIn,
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output logic [31:0] GPIOPinsOut, GPIOPinsEn,
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input logic UARTSin,
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output logic UARTSout,
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// to instruction memory *** remove later
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output logic [`XLEN-1:0] PCF,
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input logic [31:0] InstrF,
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input logic [`AHBW-1:0] HRDATA // from AHB mux in uncore
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);
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// Uncore signals
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logic HREADY, HRESP;
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logic InstrAccessFaultF, DataAccessFaultM;
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logic TimerIntM, SwIntM; // from CLINT
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logic ExtIntM = 0; // not yet connected
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// for now, seem to need these to be like this
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// until we get a better idea
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assign HREADY = 1;
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assign HRESP = 0;
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assign InstrAccessFaultF = 0;
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assign DataAccessFaultM = 0;
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// instantiate processor and memories
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wallypipelinedhart hart(.*);
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//imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished***
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//uncore uncore(.HWDATAIN(HWDATA), .*);
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endmodule
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@ -24,19 +24,15 @@ module testbench_busybear();
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic UARTSout;
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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assign HREADY = 1;
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assign HRESP = 0;
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assign HRDATA = 0;
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// for now, seem to need these to be zero until we get a better idea
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assign InstrAccessFaultF = 0;
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assign DataAccessFaultM = 0;
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// instantiate processor and memories
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wallypipelinedhart dut(.*);
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wallypipelinedsocbusybear dut(.*);
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// initialize test
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initial
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@ -103,26 +99,32 @@ module testbench_busybear();
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end
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end
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logic[63:0] adrTranslation[4:0];
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string translationType[4:0] = {"rf", "writeAdr", "PCW", "PC", "readAdr"};
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integer warningCount = 0;
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initial begin
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for(int i=0; i<5; i++) begin
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adrTranslation[i] = 64'b0;
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end
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end
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//logic[63:0] adrTranslation[4:0];
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//string translationType[4:0] = {"rf", "writeAdr", "PCW", "PC", "readAdr"};
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//initial begin
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// for(int i=0; i<5; i++) begin
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// adrTranslation[i] = 64'b0;
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// end
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//end
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//function logic equal(logic[63:0] adr, logic[63:0] adrExpected, integer func);
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// if (adr[11:0] !== adrExpected[11:0]) begin
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// equal = 1'b0;
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// end else begin
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// equal = 1'b1;
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// if ((adr+adrTranslation[func]) !== adrExpected) begin
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// adrTranslation[func] = adrExpected - adr;
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// $display("warning: probably new address translation %x for %s at instr %0d", adrTranslation[func], translationType[func], instrs);
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// warningCount += 1;
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// end
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// end
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//endfunction
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// pretty sure this isn't necessary anymore, but keeping this for now since its easier
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function logic equal(logic[63:0] adr, logic[63:0] adrExpected, integer func);
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if (adr[11:0] !== adrExpected[11:0]) begin
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equal = 1'b0;
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end else begin
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equal = 1'b1;
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if ((adr+adrTranslation[func]) !== adrExpected) begin
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adrTranslation[func] = adrExpected - adr;
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$display("warning: probably new address translation %x for %s at instr %0d", adrTranslation[func], translationType[func], instrs);
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warningCount += 1;
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end
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end
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equal = adr === adrExpected;
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endfunction
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@ -138,11 +140,11 @@ module testbench_busybear();
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genvar i;
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generate
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for(i=1; i<32; i++) begin
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always @(dut.ieu.dp.regf.rf[i]) begin
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always @(dut.hart.ieu.dp.regf.rf[i]) begin
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if ($time == 0) begin
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scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
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if (dut.ieu.dp.regf.rf[i] != regExpected) begin
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$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.ieu.dp.regf.rf[i], regExpected);
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if (dut.hart.ieu.dp.regf.rf[i] != regExpected) begin
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$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
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`ERROR
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end
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end else begin
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@ -152,13 +154,13 @@ module testbench_busybear();
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$display("%t ps, instr %0d: wrong register changed: %0d, %0d expected", $time, instrs, i, regNumExpected);
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`ERROR
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end
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if (~equal(dut.ieu.dp.regf.rf[i],regExpected, 0)) begin
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$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.ieu.dp.regf.rf[i], regExpected);
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if (~equal(dut.hart.ieu.dp.regf.rf[i],regExpected, 0)) begin
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$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
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`ERROR
|
||||
end
|
||||
if (dut.ieu.dp.regf.rf[i] !== regExpected) begin
|
||||
force dut.ieu.dp.regf.rf[i] = regExpected;
|
||||
release dut.ieu.dp.regf.rf[i];
|
||||
if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin
|
||||
force dut.hart.ieu.dp.regf.rf[i] = regExpected;
|
||||
release dut.hart.ieu.dp.regf.rf[i];
|
||||
end
|
||||
end
|
||||
end
|
||||
@ -167,8 +169,8 @@ module testbench_busybear();
|
||||
|
||||
logic [`XLEN-1:0] readAdrExpected;
|
||||
// this might need to change
|
||||
always @(dut.MemRWM[1] or HADDR) begin
|
||||
if (dut.MemRWM[1]) begin
|
||||
always @(dut.hart.MemRWM[1] or HADDR) begin
|
||||
if (dut.hart.MemRWM[1]) begin
|
||||
if($feof(data_file_memR)) begin
|
||||
$display("no more memR data to read");
|
||||
`ERROR
|
||||
@ -246,9 +248,9 @@ module testbench_busybear();
|
||||
end \
|
||||
end
|
||||
`define CHECK_CSR(CSR) \
|
||||
`CHECK_CSR2(CSR, dut.priv.csr)
|
||||
`define CSRM dut.priv.csr.genblk1.csrm
|
||||
`define CSRS dut.priv.csr.genblk1.csrs.genblk1
|
||||
`CHECK_CSR2(CSR, dut.hart.priv.csr)
|
||||
`define CSRM dut.hart.priv.csr.genblk1.csrm
|
||||
`define CSRS dut.hart.priv.csr.genblk1.csrs.genblk1
|
||||
|
||||
//`CHECK_CSR(FCSR)
|
||||
`CHECK_CSR2(MCAUSE, `CSRM)
|
||||
@ -286,8 +288,8 @@ module testbench_busybear();
|
||||
string PCtextW, PCtext2W;
|
||||
logic [31:0] InstrWExpected;
|
||||
logic [63:0] PCWExpected;
|
||||
always @(dut.ifu.PCW or dut.ieu.InstrValidW) begin
|
||||
if(dut.ieu.InstrValidW && dut.ifu.PCW != 0) begin
|
||||
always @(dut.hart.ifu.PCW or dut.hart.ieu.InstrValidW) begin
|
||||
if(dut.hart.ieu.InstrValidW && dut.hart.ifu.PCW != 0) begin
|
||||
if($feof(data_file_PCW)) begin
|
||||
$display("no more PC data to read");
|
||||
`ERROR
|
||||
@ -300,8 +302,8 @@ module testbench_busybear();
|
||||
scan_file_PCW = $fscanf(data_file_PCW, "%x\n", InstrWExpected);
|
||||
// then expected PC value
|
||||
scan_file_PCW = $fscanf(data_file_PCW, "%x\n", PCWExpected);
|
||||
if(~equal(dut.ifu.PCW,PCWExpected,2)) begin
|
||||
$display("%t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.ifu.PCW, PCWExpected);
|
||||
if(~equal(dut.hart.ifu.PCW,PCWExpected,2)) begin
|
||||
$display("%t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.hart.ifu.PCW, PCWExpected);
|
||||
`ERROR
|
||||
end
|
||||
//if(it.InstrW != InstrWExpected) begin
|
||||
@ -384,9 +386,9 @@ module testbench_busybear();
|
||||
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
||||
logic [31:0] InstrW;
|
||||
instrNameDecTB dec(InstrF, InstrFName);
|
||||
instrTrackerTB it(clk, reset, dut.ieu.dp.FlushE,
|
||||
dut.ifu.InstrD, dut.ifu.InstrE,
|
||||
dut.ifu.InstrM, InstrW,
|
||||
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
|
||||
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, InstrW,
|
||||
InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
// generate clock to sequence tests
|
||||
|
||||
Loading…
Reference in New Issue
Block a user