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Implemented fix disucssed with Elizabeth

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This commit is contained in:
Teo Ene 2021-03-03 18:17:53 -06:00
parent 4562c61af3
commit 6031269de8
2 changed files with 13 additions and 10 deletions
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20
wally-pipelined/regression/wally-coremark.do
View File

@ -52,23 +52,23 @@ add wave -divider
#add wave /testbench/dut/hart/FlushM
#add wave /testbench/dut/hart/FlushW
add wave -divider
add wave -divider Fetch
add wave -hex /testbench/dut/hart/ifu/PCF
add wave -hex /testbench/dut/hart/ifu/InstrF
add wave /testbench/InstrFName
add wave -divider
add wave -divider Decode
add wave -hex /testbench/dut/hart/ifu/PCD
add wave -hex /testbench/dut/hart/ifu/InstrD
add wave /testbench/InstrDName
add wave -divider
add wave -divider Execute
add wave -hex /testbench/dut/hart/ifu/PCE
add wave -hex /testbench/dut/hart/ifu/InstrE
add wave /testbench/InstrEName
add wave -divider
add wave -divider Memory
add wave -hex /testbench/dut/hart/ifu/PCM
add wave -hex /testbench/dut/hart/ifu/InstrM
add wave /testbench/InstrMName
add wave -divider
add wave -divider Write
add wave -hex /testbench/dut/hart/ifu/PCW
add wave -hex /testbench/dut/hart/ifu/InstrW
add wave /testbench/InstrWName
@ -76,7 +76,7 @@ add wave /testbench/InstrWName
#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
#add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
#add wave /testbench/dut/hart/ieu/dp/PCSrcE
add wave -divider
add wave -divider Regfile
#add wave /testbench/dut/uncore/dtim/memwrite
#add wave -hex /testbench/dut/uncore/HADDR
#add wave -hex /testbench/dut/uncore/HWDATA
@ -88,9 +88,9 @@ add wave -divider
#add wave -hex /testbench/dut/hart/ieu/dp/RdW
#add wave -hex -r /testbench/*
add wave -hex -r /testbench/dut/hart/ieu/dp/regf/*
add wave -divider Misc
add wave -divider
add wave -divider
add wave -hex -r /testbench/dut/hart/ebu/ReadDataW
#add wave -hex -r /testbench/dut/uncore/dtim/RAM
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
@ -106,6 +106,6 @@ configure wave -childrowmargin 2
set DefaultRadix hexadecimal
-- Run the Simulation
run 3000
#run -all
#run 3000
run -all
#quit

3
wally-pipelined/testbench/testbench-coremark.sv
View File

@ -66,6 +66,7 @@ module testbench();
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
// initialize tests
integer j;
initial
begin
totalerrors = 0;
@ -73,6 +74,8 @@ module testbench();
memfilename = tests[0];
$readmemh(memfilename, dut.imem.RAM);
$readmemh(memfilename, dut.uncore.dtim.RAM);
for(j=1911; j < 65535; j = j+1)
dut.uncore.dtim.RAM[j] = 64'b0;
reset = 1; # 22; reset = 0;
end
// generate clock to sequence tests