forked from Github_Repos/cvw
Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler. |
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| .. | ||
| bin | ||
| config | ||
| regression | ||
| src | ||
| testbench | ||
| testgen | ||
| lint-wally | ||