forked from Github_Repos/cvw
Added explicit names to lsu, lsuarb and pagetable walker to make the code refactoring process eaiser.
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Ross Thompson
parent
cf688bd3f6
commit
043f1e10c5
@ -66,7 +66,7 @@ module lsu (
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input logic MemAckW, // from ahb
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input logic [`XLEN-1:0] HRDATAW, // from ahb
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output logic [2:0] Funct3MfromLSU,
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output logic StallWfromLSU,
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output logic StallWfromLSU,
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// mmu management
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@ -85,14 +85,14 @@ module lsu (
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output logic DTLBHitM, // not connected
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// PMA/PMP (inside mmu) signals
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input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well.
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input logic [2:0] HSIZE, HBURST,
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input logic HWRITE,
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input var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker.
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input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well.
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input logic [2:0] HSIZE, HBURST,
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input logic HWRITE,
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input var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker.
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output logic PMALoadAccessFaultM, PMAStoreAccessFaultM,
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output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa.
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output logic PMALoadAccessFaultM, PMAStoreAccessFaultM,
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output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa.
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output logic DSquashBusAccessM
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// output logic [5:0] DHSELRegionsM
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@ -122,8 +122,8 @@ module wallypipelinedhart
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logic PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM;
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logic PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM;
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logic DSquashBusAccessM, ISquashBusAccessF;
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var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
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var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0];
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var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
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var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0];
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// IMem stalls
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logic ICacheStallF;
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@ -187,10 +187,38 @@ module wallypipelinedhart
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// mux2 #(`XLEN) OutputInput2mux(WriteDataM, FWriteDataM, FMemRWM[0], WriteDatatmpM);
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pagetablewalker pagetablewalker(.HPTWRead(HPTWRead),
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.*); // can send addresses to ahblite, send out pagetablestall
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pagetablewalker pagetablewalker(
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.clk(clk),
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.reset(reset),
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.SATP_REGW(SATP_REGW), // already on lsu port
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.PCF(PCF), // add to lsu port
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.MemAdrM(MemAdrM), // alreayd on lsu port
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.ITLBMissF(ITLBMissF), // add to lsu port
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.DTLBMissM(DTLBMissM), // already on lsu port convert to internal
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.MemRWM(MemRWM), // already on lsu port
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.PageTableEntryF(PageTableEntryF), // add to lsu port
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.PageTableEntryM(PageTableEntryM), // already on lsu port convert to internal
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.PageTypeF(PageTypeF), // add to lsu port connects to ifu
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.PageTypeM(PageTypeM),
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.ITLBWriteF(ITLBWriteF),
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.DTLBWriteM(DTLBWriteM),
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.MMUReadPTE(MMUReadPTE),
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.MMUReady(MMUReady),
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.HPTWStall(HPTWStall),
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.MMUPAdr(MMUPAdr),
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.MMUTranslate(MMUTranslate),
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.HPTWRead(HPTWRead),
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.MMUStall(MMUStall),
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.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
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.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
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.WalkerStorePageFaultM(WalkerStorePageFaultM));
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// arbiter between IEU and pagetablewalker
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lsuArb arbiter(// HPTW connection
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lsuArb arbiter(.clk(clk),
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.reset(reset),
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// HPTW connection
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.HPTWTranslate(MMUTranslate),
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.HPTWRead(HPTWRead),
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.HPTWPAdr(MMUPAdr),
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@ -202,8 +230,8 @@ module wallypipelinedhart
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.Funct3M(Funct3M),
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.AtomicM(AtomicM),
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.MemAdrM(MemAdrM),
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.StallW(StallW),
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.WriteDataM(WriteDataM),
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.StallW(StallW),
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.ReadDataW(ReadDataW),
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.CommittedM(CommittedM),
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.SquashSCW(SquashSCW),
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@ -222,29 +250,78 @@ module wallypipelinedhart
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.DataMisalignedMfromLSU(DataMisalignedMfromLSU),
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.ReadDataWFromLSU(ReadDataWFromLSU),
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.HPTWReadyfromLSU(HPTWReadyfromLSU),
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.DataStall(DataStall),
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.*);
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.DataStall(DataStall));
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lsu lsu(.MemRWM(MemRWMtoLSU),
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.Funct3M(Funct3MtoLSU),
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.AtomicM(AtomicMtoLSU),
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.MemAdrM(MemAdrMtoLSU),
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.WriteDataM(WriteDataMtoLSU),
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.ReadDataW(ReadDataWFromLSU),
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lsu lsu(.clk(clk),
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.reset(reset),
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.StallM(StallM),
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.FlushM(FlushM),
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.StallW(StallWtoLSU),
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.FlushW(FlushW),
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// connected to arbiter (reconnect to CPU)
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.MemRWM(MemRWMtoLSU), // change to MemRWM
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.Funct3M(Funct3MtoLSU), // change to Funct3M
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.AtomicM(AtomicMtoLSU), // change to AtomicMtoLSU
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.CommittedM(CommittedMfromLSU), // change to CommitttedM
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.SquashSCW(SquashSCWfromLSU), // change to SquashSCW
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.DataMisalignedM(DataMisalignedMfromLSU), // change to DataMisalignedM
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.MemAdrM(MemAdrMtoLSU), // change to MemAdrM
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.WriteDataM(WriteDataMtoLSU), // change to WriteDataM
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.ReadDataW(ReadDataWFromLSU), // change to ReadDataW
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.CommittedM(CommittedMfromLSU),
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.SquashSCW(SquashSCWfromLSU),
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.DataMisalignedM(DataMisalignedMfromLSU),
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.DisableTranslation(DisableTranslation),
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// connected to ahb (all stay the same)
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.CommitM(CommitM),
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.MemPAdrM(MemPAdrM),
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.MemReadM(MemReadM),
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.MemWriteM(MemWriteM),
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.AtomicMaskedM(AtomicMaskedM),
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.MemAckW(MemAckW),
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.HRDATAW(HRDATAW),
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.Funct3MfromLSU(Funct3MfromLSU), // stays the same
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.StallWfromLSU(StallWfromLSU), // stays the same
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.DSquashBusAccessM(DSquashBusAccessM), // probalby removed after dcache implemenation?
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// currently not connected (but will need to be used for lsu talking to ahb.
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.HADDR(HADDR),
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.HSIZE(HSIZE),
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.HBURST(HBURST),
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.HWRITE(HWRITE),
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// connect to csr or privilege and stay the same.
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.PrivilegeModeW(PrivilegeModeW), // connects to csr
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.PMPCFG_ARRAY_REGW(PMPCFG_ARRAY_REGW), // connects to csr
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.PMPADDR_ARRAY_REGW(PMPADDR_ARRAY_REGW), // connects to csr
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// hptw keep i/o
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.SATP_REGW(SATP_REGW), // from csr
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.STATUS_MXR(STATUS_MXR), // from csr
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.STATUS_SUM(STATUS_SUM), // from csr
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.DTLBFlushM(DTLBFlushM), // connects to privilege
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.NonBusTrapM(NonBusTrapM), // connects to privilege
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.DTLBLoadPageFaultM(DTLBLoadPageFaultM), // connects to privilege
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.DTLBStorePageFaultM(DTLBStorePageFaultM), // connects to privilege
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.LoadMisalignedFaultM(LoadMisalignedFaultM), // connects to privilege
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.LoadAccessFaultM(LoadAccessFaultM), // connects to privilege
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.StoreMisalignedFaultM(StoreMisalignedFaultM), // connects to privilege
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.StoreAccessFaultM(StoreAccessFaultM), // connects to privilege
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.PMALoadAccessFaultM(PMALoadAccessFaultM),
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.PMAStoreAccessFaultM(PMAStoreAccessFaultM),
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.PMPLoadAccessFaultM(PMPLoadAccessFaultM),
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.PMPStoreAccessFaultM(PMPStoreAccessFaultM),
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// connected to hptw. Move to internal.
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.PageTableEntryM(PageTableEntryM),
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.PageTypeM(PageTypeM),
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.DTLBWriteM(DTLBWriteM), // from hptw.
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.DTLBMissM(DTLBMissM), // to hptw from dmmu
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.DisableTranslation(DisableTranslation), // from hptw to dmmu
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.HPTWReady(HPTWReadyfromLSU), // from hptw, remove
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.DTLBHitM(DTLBHitM), // not connected remove
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.DataStall(DataStall)) // change to DCacheStall
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;
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.DataStall(DataStall),
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.HPTWReady(HPTWReadyfromLSU),
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.Funct3MfromLSU(Funct3MfromLSU),
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.StallWfromLSU(StallWfromLSU),
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// .DataStall(LSUStall),
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.* ); // data cache unit
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ahblite ebu(
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//.InstrReadF(1'b0),
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