David Harris 58ce0fbbcc Flush uart print statements on \n		2021-05-03 19:37:45 -04:00
..
bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	fixed subtle typo in icache fsm. Was messing up hit spill hit.	2021-05-03 16:55:36 -05:00
misc/tlb_toy	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-03 16:56:00 -05:00
src	Flush uart print statements on \n	2021-05-03 19:37:45 -04:00
testbench	Extended maximum signature length to 1M	2021-05-03 15:29:20 -04:00
testgen	Add machine-mode timer interrupts to mcause tests	2021-04-29 16:39:18 -04:00
lint-wally	Add lint to regression	2021-05-03 17:32:05 -04:00