Ross Thompson 7f38056879 fixed subtle typo in icache fsm. Was messing up hit spill hit. ... I believe the mibench qsort benchmark runs after this icache fix.		2021-05-03 16:55:36 -05:00
..
bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	fixed subtle typo in icache fsm. Was messing up hit spill hit.	2021-05-03 16:55:36 -05:00
misc/tlb_toy	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	fixed subtle typo in icache fsm. Was messing up hit spill hit.	2021-05-03 16:55:36 -05:00
src	fixed subtle typo in icache fsm. Was messing up hit spill hit.	2021-05-03 16:55:36 -05:00
testbench	Extended maximum signature length to 1M	2021-05-03 15:29:20 -04:00
testgen	Add machine-mode timer interrupts to mcause tests	2021-04-29 16:39:18 -04:00
lint-wally	Enhance lint-wally functionality	2021-04-29 14:48:41 -04:00