Debugging instruction fetch

wally-pipelined/regression/wally-pipelined.do

@@ -62,26 +62,27 @@ add wave -divider
 add wave -hex /testbench/dut/hart/ifu/PCF
 add wave -hex /testbench/dut/hart/ifu/InstrF
 add wave /testbench/InstrFName
-#add wave -hex /testbench/dut/hart/ifu/PCD
+add wave -hex /testbench/dut/hart/ifu/PCD
 add wave -hex /testbench/dut/hart/ifu/InstrD
 add wave /testbench/InstrDName
 add wave -divider
-#add wave -hex /testbench/dut/hart/ifu/PCE
-#add wave -hex /testbench/dut/hart/ifu/InstrE
+add wave -hex /testbench/dut/hart/ifu/PCE
+add wave -hex /testbench/dut/hart/ifu/InstrE
 add wave /testbench/InstrEName
 add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
 add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
 add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
 add wave /testbench/dut/hart/ieu/dp/PCSrcE
 add wave -divider
-#add wave -hex /testbench/dut/hart/ifu/PCM
-#add wave -hex /testbench/dut/hart/ifu/InstrM
+add wave -hex /testbench/dut/hart/ifu/PCM
+add wave -hex /testbench/dut/hart/ifu/InstrM
 add wave /testbench/InstrMName
 add wave /testbench/dut/uncore/dtim/memwrite
 add wave -hex /testbench/dut/uncore/HADDR
 add wave -hex /testbench/dut/uncore/HWDATA
 add wave -divider
 add wave -hex /testbench/dut/hart/ifu/PCW
+add wave -hex /testbench/dut/hart/ifu/InstrW
 add wave /testbench/InstrWName
 add wave /testbench/dut/hart/ieu/dp/RegWriteW
 add wave -hex /testbench/dut/hart/ieu/dp/ResultW

wally-pipelined/src/ebu/ahblite.sv

@@ -38,6 +38,7 @@ module ahblite (
   // Signals from Instruction Cache
   input  logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram
   input  logic             InstrReadF,
+  input  logic             ResolveBranchD,
   output logic [31:0] InstrRData,
 //  output logic             IReady,
   // Signals from Data Cache
@@ -158,7 +159,8 @@ module ahblite (
     else InstrState <= NextInstrState;*/
 
   assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM  && ~MemWriteM && InstrReadF)) || 
-                          (InstrState == 1 && ~InstrAckD);
+                          (InstrState == 1 && ~InstrAckD) ||
+                          (InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing 
   assign InstrStall = NextInstrState | MemState | NextMemState; // *** check this, explain better
   // temporarily turn off stalls and check it works
   //assign DataStall = 0;

wally-pipelined/src/ifu/ifu.sv

@@ -37,6 +37,7 @@ module ifu (
   output logic             InstrReadF,
   // Decode  
   //output logic             InstrStall,
+  output logic             ResolveBranchD,
   // Execute
   input  logic             PCSrcE, 
   input  logic [`XLEN-1:0] PCTargetE,
@@ -66,12 +67,15 @@ module ifu (
 
   // *** put memory interface on here, InstrF becomes output
   assign InstrPAdrF = PCF; // *** no MMU
-  assign InstrReadF = ~StallD;
+  assign InstrReadF = ~StallD; // *** & ICacheMissF; add later
 
   assign PrivilegedChangePCM = RetM | TrapM;
 
   assign StallExceptResolveBranchesF = StallF & ~(PCSrcE | PrivilegedChangePCM);
 
+  // dh 2/8/2022 keep in instruction fetch stall mode when taking branch
+  flopr #(1) rbreg(clk, reset, (PCSrcE | PrivilegedChangePCM), ResolveBranchD);
+
   mux3    #(`XLEN) pcmux(PCPlus2or4F, PCTargetE, PrivilegedNextPCM, {PrivilegedChangePCM, PCSrcE}, UnalignedPCNextF);
   assign  PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
   flopenl #(`XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, `RESET_VECTOR, PCF);

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -29,7 +29,7 @@
 module wallypipelinedhart (
   input  logic             clk, reset,
   output logic [`XLEN-1:0] PCF,
-  input  logic [31:0]      InstrF,
+//  input  logic [31:0]      InstrF,
   // Privileged
   input  logic             TimerIntM, ExtIntM, SwIntM,
   input  logic             InstrAccessFaultF, 
@@ -60,7 +60,7 @@ module wallypipelinedhart (
   // new signals that must connect through DP
   logic        CSRWriteM, PrivilegedM;
   logic [`XLEN-1:0] SrcAM;
-//  logic [31:0] InstrF;
+  logic [31:0] InstrF;
   logic [31:0] InstrD, InstrM;
   logic [`XLEN-1:0] PCE, PCM, PCLinkW;
   logic [`XLEN-1:0] PCTargetE;
@@ -75,6 +75,7 @@ module wallypipelinedhart (
   logic StoreMisalignedFaultM, StoreAccessFaultM;
   logic [`XLEN-1:0] InstrMisalignedAdrM;
   logic [`XLEN-1:0] zero = 0;
+  logic ResolveBranchD;
 
   logic        PCSrcE;
   logic        CSRWritePendingDEM;
@@ -98,20 +99,20 @@ module wallypipelinedhart (
   ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller
   dmem dmem(.*); // data cache unit
 
-/*
+
   ahblite ebu( 
     //.InstrReadF(1'b0),
     .InstrRData(InstrF), // hook up InstrF later
     .MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]),
     .*);
-*/
+
 // changing from this to the line above breaks the program.  auipc at 104 fails; seems to be flushed.
 // Would need to insertinstruction as InstrD, not InstrF
-  ahblite ebu( 
-    .InstrReadF(1'b0),
+    /*ahblite ebu( 
+  .InstrReadF(1'b0),
     .InstrRData(), // hook up InstrF later
     .MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]),
-    .*);
+    .*); */
 
 /*  
   mdu mdu(.*); // multiply and divide unit

wally-pipelined/testbench/testbench-imperas.sv

@@ -75,7 +75,6 @@ string tests64iNOc[] = {
                      "rv64i/I-MISALIGN_JMP-01","2000"
   };
  string tests64i[] = '{                 
-                     "rv64i/I-ENDIANESS-01", "2010",
                      "rv64i/I-ADD-01", "3000",
                      "rv64i/I-ADDI-01", "3000",
                      "rv64i/I-ADDIW-01", "3000",
@@ -261,9 +260,9 @@ string tests32i[] = {
 
   // Track names of instructions
   instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
-                dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
+                dut.hart.ifu.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
                 dut.hart.ifu.InstrM,  dut.hart.ifu.InstrW,
-                InstrDName, InstrEName, InstrMName, InstrWName);
+                InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
 
   // initialize tests
   initial
@@ -366,15 +365,16 @@ endmodule
 
 module instrTrackerTB(
   input  logic            clk, reset, FlushE,
-  input  logic [31:0]     InstrD,
+  input  logic [31:0]     InstrF, InstrD,
   input  logic [31:0]     InstrE, InstrM,
   input  logic [31:0]     InstrW,
 //  output logic [31:0]     InstrW,
-  output string           InstrDName, InstrEName, InstrMName, InstrWName);
+  output string           InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
         
   // stage Instr to Writeback for visualization
   // flopr  #(32) InstrWReg(clk, reset, InstrM, InstrW);
 
+  instrNameDecTB fdec(InstrF, InstrFName);
   instrNameDecTB ddec(InstrD, InstrDName);
   instrNameDecTB edec(InstrE, InstrEName);
   instrNameDecTB mdec(InstrM, InstrMName);