forked from Github_Repos/cvw
Clean up MMU code
This commit is contained in:
Thomas Fleming
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682bc7b58e
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136
wally-pipelined/misc/lzd.sv
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136
wally-pipelined/misc/lzd.sv
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@ -0,0 +1,136 @@
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// V. G. Oklobdzija, "Algorithmic design of a hierarchical and modular
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// leading zero detector circuit," in Electronics Letters, vol. 29,
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// no. 3, pp. 283-284, 4 Feb. 1993, doi: 10.1049/el:19930193.
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module lz2 (P, V, B0, B1);
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input logic B0;
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input logic B1;
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output logic P;
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output logic V;
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assign V = B0 | B1;
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assign P = B0 & ~B1;
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endmodule // lz2
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// Note: This module is not made out of two lz2's - why not? (MJS)
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module lz4 (ZP, ZV, B0, B1, V0, V1);
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output logic [1:0] ZP;
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output logic ZV;
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input logic B0;
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input logic B1;
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input logic V0;
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input logic V1;
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assign ZP[0] = V0 ? B0 : B1;
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assign ZP[1] = ~V0;
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assign ZV = V0 | V1;
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endmodule // lz4
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// Note: This module is not made out of two lz4's - why not? (MJS)
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module lz8 (ZP, ZV, B);
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input logic [7:0] B;
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output logic [2:0] ZP;
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output logic ZV;
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logic s1p0;
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logic s1v0;
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logic s1p1;
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logic s1v1;
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logic s2p0;
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logic s2v0;
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logic s2p1;
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logic s2v1;
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logic [1:0] ZPa;
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logic [1:0] ZPb;
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logic ZVa;
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logic ZVb;
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lz2 l1(s1p0, s1v0, B[2], B[3]);
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lz2 l2(s1p1, s1v1, B[0], B[1]);
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lz4 l3(ZPa, ZVa, s1p0, s1p1, s1v0, s1v1);
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lz2 l4(s2p0, s2v0, B[6], B[7]);
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lz2 l5(s2p1, s2v1, B[4], B[5]);
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lz4 l6(ZPb, ZVb, s2p0, s2p1, s2v0, s2v1);
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assign ZP[1:0] = ZVb ? ZPb : ZPa;
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assign ZP[2] = ~ZVb;
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assign ZV = ZVa | ZVb;
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endmodule // lz8
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module lz16 (ZP, ZV, B);
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input logic [15:0] B;
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output logic [3:0] ZP;
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output logic ZV;
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logic [2:0] ZPa;
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logic [2:0] ZPb;
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logic ZVa;
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logic ZVb;
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lz8 l1(ZPa, ZVa, B[7:0]);
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lz8 l2(ZPb, ZVb, B[15:8]);
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assign ZP[2:0] = ZVb ? ZPb : ZPa;
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assign ZP[3] = ~ZVb;
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assign ZV = ZVa | ZVb;
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endmodule // lz16
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module lz32 (ZP, ZV, B);
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input logic [31:0] B;
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output logic [4:0] ZP;
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output logic ZV;
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logic [3:0] ZPa;
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logic [3:0] ZPb;
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logic ZVa;
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logic ZVb;
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lz16 l1(ZPa, ZVa, B[15:0]);
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lz16 l2(ZPb, ZVb, B[31:16]);
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assign ZP[3:0] = ZVb ? ZPb : ZPa;
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assign ZP[4] = ~ZVb;
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assign ZV = ZVa | ZVb;
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endmodule // lz32
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// This module returns the number of leading zeros ZP in the 64-bit
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// number B. If there are no ones in B, then ZP and ZV are both 0.
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module lz64 (ZP, ZV, B);
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input logic [63:0] B;
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output logic [5:0] ZP;
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output logic ZV;
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logic [4:0] ZPa;
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logic [4:0] ZPb;
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logic ZVa;
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logic ZVb;
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lz32 l1(ZPa, ZVa, B[31:0]);
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lz32 l2(ZPb, ZVb, B[63:32]);
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assign ZV = ZVa | ZVb;
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assign ZP[4:0] = (ZVb ? ZPb : ZPa) & {5{ZV}};
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assign ZP[5] = ~ZVb & ZV;
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endmodule // lz64
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@ -1,58 +0,0 @@
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`include "wally-config.vh"
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module tlb_testbench();
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logic clk, reset;
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// DUT inputs
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logic [`XLEN-1:0] SATP;
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logic [`XLEN-1:0] VirtualAddress;
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logic [`XLEN-1:0] PageTableEntryWrite;
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logic TLBWrite, TLBFlush;
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// DUT outputs
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logic [`XLEN-1:0] PhysicalAddress;
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logic TLBMiss, TLBHit;
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// Testbench signals
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logic [33:0] expected;
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logic [31:0] vectornum, errors;
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logic [99:0] testvectors[10000:0];
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assign SATP = {1'b1, 31'b0};
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// instantiate device under test
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tlb_toy dut(.*);
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// generate clock
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always begin
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clk=1; #5; clk=0; #5;
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end
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// at start of test, load vectors and pulse reset
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initial begin
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$readmemb("tlb_toy.tv", testvectors);
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vectornum = 0; errors = 0; reset = 1; #22; reset = 0;
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end
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// apply test vectors on rising edge of clk
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always @(posedge clk) begin
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#1; {VirtualAddress, PageTableEntryWrite, TLBWrite, TLBFlush, expected} = testvectors[vectornum];
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end
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// check results on falling edge of clk
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always @(negedge clk)
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if (~reset) begin // skip during reset
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if ({PhysicalAddress, TLBMiss, TLBHit} !== expected) begin // check result
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$display("Error: VirtualAddress = %b, write = %b, data = %b, flush = %b", VirtualAddress,
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TLBWrite, PageTableEntryWrite, TLBFlush);
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$display(" outputs = %b %b %b (%b expected)",
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PhysicalAddress, TLBMiss, TLBHit, expected);
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errors = errors + 1;
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end
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vectornum = vectornum + 1;
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if (testvectors[vectornum] === 100'bx) begin
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$display("%d tests completed with %d errors", vectornum, errors);
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$stop;
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end
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end
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endmodule
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@ -1,233 +0,0 @@
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///////////////////////////////////////////
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// tlb_toy.sv
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//
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// Written: jtorrey@hmc.edu 16 February 2021
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// Modified:
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//
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// Purpose: Example translation lookaside buffer
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// Cache of virtural-to-physical address translations
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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/**
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* sv32 specs
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* ----------
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* Virtual address [31:0] (32 bits)
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* [________________________________]
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* |--VPN1--||--VPN0--||----OFF---|
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* 10 10 12
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*
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* Physical address [33:0] (34 bits)
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* [__________________________________]
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* |---PPN1---||--PPN0--||----OFF---|
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* 12 10 12
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*
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* Page Table Entry [31:0] (32 bits)
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* [________________________________]
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* |---PPN1---||--PPN0--|||DAGUXWRV
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* 12 10 ^^
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* RSW(2) -- for OS
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*/
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/* *** TODO:
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* - add LRU algorithm (select the write index based on which entry was used
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* least recently)
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*/
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// The TLB will have 2**ENTRY_BITS total entries
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module tlb_toy #(parameter ENTRY_BITS = 3) (
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input clk, reset,
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// Current value of satp CSR (from privileged unit)
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input [`XLEN-1:0] SATP, // *** How do we get this?
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// Virtual address input
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input [`XLEN-1:0] VirtualAddress,
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// Controls for writing a new entry to the TLB
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input [`XLEN-1:0] PageTableEntryWrite,
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input TLBWrite,
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// Invalidate all TLB entries
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input TLBFlush,
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// Physical address outputs
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output [`XLEN-1:0] PhysicalAddress,
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output TLBMiss,
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output TLBHit
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);
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generate
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if (`XLEN == 32) begin: ARCH
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localparam VPN_BITS = 20;
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localparam PPN_BITS = 22;
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localparam PA_BITS = 34;
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logic SvMode;
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assign SvMode = SATP[31]; // *** change to an enum somehow?
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end else begin: ARCH
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localparam VPN_BITS = 27;
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localparam PPN_BITS = 44;
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localparam PA_BITS = 56;
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logic SvMode; // currently just a boolean whether translation enabled
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assign SvMode = SATP[63]; // *** change to an enum somehow?
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end
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endgenerate
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// Index (currently random) to write the next TLB entry
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logic [ENTRY_BITS-1:0] WriteIndex;
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// Sections of the virtual and physical addresses
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logic [ARCH.VPN_BITS-1:0] VirtualPageNumber;
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logic [ARCH.PPN_BITS-1:0] PhysicalPageNumber;
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logic [11:0] PageOffset;
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logic [ARCH.PA_BITS-1:0] PhysicalAddressFull;
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// Pattern and pattern location in the CAM
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logic [ENTRY_BITS-1:0] VPNIndex;
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// RAM access location
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logic [ENTRY_BITS-1:0] EntryIndex;
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// Page table entry matching the virtual address
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logic [`XLEN-1:0] PageTableEntry;
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assign VirtualPageNumber = VirtualAddress[ARCH.VPN_BITS+11:12];
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assign PageOffset = VirtualAddress[11:0];
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// Choose a read or write location to the entry list
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mux2 #(3) indexmux(VPNIndex, WriteIndex, TLBWrite, EntryIndex);
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// Currently use random replacement algorithm
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tlb_rand rdm(.*);
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tlb_ram #(ENTRY_BITS) ram(.*);
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tlb_cam #(ENTRY_BITS, ARCH.VPN_BITS) cam(.*);
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always_comb begin
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assign PhysicalPageNumber = PageTableEntry[ARCH.PPN_BITS+9:10];
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if (TLBHit) begin
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assign PhysicalAddressFull = {PhysicalPageNumber, PageOffset};
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end else begin
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assign PhysicalAddressFull = 8'b0; // *** Actual behavior; disabled until walker functioning
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//assign PhysicalAddressFull = {2'b0, VirtualPageNumber, PageOffset} // *** pass through should be removed as soon as walker ready
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end
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end
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generate
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if (`XLEN == 32) begin
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mux2 #(`XLEN) addressmux(VirtualAddress, PhysicalAddressFull[31:0], ARCH.SvMode, PhysicalAddress);
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end else begin
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mux2 #(`XLEN) addressmux(VirtualAddress, {8'b0, PhysicalAddressFull}, ARCH.SvMode, PhysicalAddress);
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end
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endgenerate
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assign TLBMiss = ~TLBHit & ~(TLBWrite | TLBFlush) & ARCH.SvMode;
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endmodule
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module tlb_ram #(parameter ENTRY_BITS = 3) (
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input clk, reset,
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input [ENTRY_BITS-1:0] EntryIndex,
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input [`XLEN-1:0] PageTableEntryWrite,
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input TLBWrite,
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output [`XLEN-1:0] PageTableEntry
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);
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localparam NENTRIES = 2**ENTRY_BITS;
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logic [`XLEN-1:0] ram [0:NENTRIES-1];
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always @(posedge clk) begin
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if (TLBWrite) ram[EntryIndex] <= PageTableEntryWrite;
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end
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assign PageTableEntry = ram[EntryIndex];
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initial begin
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for (int i = 0; i < NENTRIES; i++)
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ram[i] = `XLEN'b0;
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end
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endmodule
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module tlb_cam #(parameter ENTRY_BITS = 3,
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parameter KEY_BITS = 20) (
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input clk, reset,
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input [KEY_BITS-1:0] VirtualPageNumber,
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input [ENTRY_BITS-1:0] WriteIndex,
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input TLBWrite,
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input TLBFlush,
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output [ENTRY_BITS-1:0] VPNIndex,
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output TLBHit
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);
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localparam NENTRIES = 2**ENTRY_BITS;
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// Each entry of this memory has KEY_BITS for the key plus one valid bit.
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logic [KEY_BITS:0] ram [0:NENTRIES-1];
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logic [ENTRY_BITS-1:0] matched_address_comb;
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logic match_found_comb;
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always @(posedge clk) begin
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if (TLBWrite) ram[WriteIndex] <= {1'b1,VirtualPageNumber};
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if (TLBFlush) begin
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for (int i = 0; i < NENTRIES; i++)
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ram[i][KEY_BITS] = 1'b0; // Zero out msb (valid bit) of all entries
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end
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end
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// *** Check whether this for loop synthesizes correctly
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always_comb begin
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match_found_comb = 1'b0;
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matched_address_comb = '0;
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for (int i = 0; i < NENTRIES; i++) begin
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if (ram[i] == {1'b1,VirtualPageNumber} && !match_found_comb) begin
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matched_address_comb = i;
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match_found_comb = 1;
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end else begin
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matched_address_comb = matched_address_comb;
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match_found_comb = match_found_comb;
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end
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end
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end
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assign VPNIndex = matched_address_comb;
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assign TLBHit = match_found_comb & ~(TLBWrite | TLBFlush);
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initial begin
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for (int i = 0; i < NENTRIES; i++)
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ram[i] <= '0;
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end
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endmodule
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module tlb_rand #(parameter ENTRY_BITS = 3) (
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input clk, reset,
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output [ENTRY_BITS:0] WriteIndex
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);
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logic [31:0] data;
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assign data = $urandom;
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assign WriteIndex = data[ENTRY_BITS:0];
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endmodule
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@ -1,11 +0,0 @@
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// tlb_toy.tv
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// PCF _ PageTableEntryF _ ITLBWriteF _ ITLBFlushF ___ PCPF _ ITLBMissF _ ITLBHitF
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10101010101010101010101010101010_00000000000000000000000000000000_0_0___00000000000000000000000000000000_1_0
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// Write test: Add translation aaaaa -> 044444 to TLB
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10101010101010101010101010101010_00010001000100010001001100110010_1_0___00000000000000000000000000000000_0_0
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10101010101010101010101010101010_00000000000000000000000000000000_0_0___01000100010001000100101010101010_0_1
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10101010101010101010101010101010_00000000000000000000000000000000_0_0___01000100010001000100101010101010_0_1
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10101010100010101010101010101010_00000000000000000000000000000000_0_0___00000000000000000000000000000000_1_0
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// Flush test: should invalidate all entries
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00000000000000000000000000000000_00000000000000000000000000000000_0_1___00000000000000000000000000000000_0_0
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10101010101010101010101010101010_00000000000000000000000000000000_0_0___00000000000000000000000000000000_1_0
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@ -54,7 +54,7 @@ module ahblite (
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// Signals from MMU
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input logic MMUStall,
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input logic [`XLEN-1:0] MMUPAdr,
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input logic MMUTranslate, MMUTranslationComplete,
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input logic MMUTranslate,
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output logic [`XLEN-1:0] MMUReadPTE,
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output logic MMUReady,
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// Signals from PMA checker
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@ -29,11 +29,7 @@
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/* ***
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TO-DO:
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- Faults have a timing issue and currently do not work.
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- Leaf state brings HADDR down to zeros (maybe fixed?)
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- Complete rv64ic case
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- Implement better accessed/dirty behavior
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- Implement read/write/execute checking (either here or in TLB)
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*/
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module pagetablewalker (
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@ -58,7 +54,6 @@ module pagetablewalker (
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// Signals to ahblite (memory addresses to access)
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output logic [`XLEN-1:0] MMUPAdr,
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output logic MMUTranslate,
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output logic MMUTranslationComplete,
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// Stall signal
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output logic MMUStall,
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@ -70,7 +65,6 @@ module pagetablewalker (
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);
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// Internal signals
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logic SvMode, TLBMiss;
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logic [`PPN_BITS-1:0] BasePageTablePPN;
|
||||
logic [`XLEN-1:0] TranslationVAdr;
|
||||
logic [`XLEN-1:0] SavedPTE, CurrentPTE;
|
||||
@ -88,37 +82,10 @@ module pagetablewalker (
|
||||
logic [`XLEN-1:0] PageTableEntry;
|
||||
logic [1:0] PageType;
|
||||
|
||||
// Signals for direct, fake translations. Not part of the final Wally version.
|
||||
logic [`XLEN-1:0] DirectInstrPTE, DirectMemPTE;
|
||||
localparam DirectPTEFlags = {2'b0, 8'b00001111};
|
||||
|
||||
logic [`VPN_BITS-1:0] PCPageNumber, MemAdrPageNumber;
|
||||
|
||||
assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
|
||||
|
||||
assign MemStore = MemRWM[0];
|
||||
|
||||
assign PCPageNumber = PCF[`VPN_BITS+11:12];
|
||||
assign MemAdrPageNumber = MemAdrM[`VPN_BITS+11:12];
|
||||
|
||||
// Create fake page table entries for direct virtual to physical translation
|
||||
generate
|
||||
if (`XLEN == 32) begin
|
||||
assign DirectInstrPTE = {PCPageNumber, DirectPTEFlags};
|
||||
assign DirectMemPTE = {MemAdrPageNumber, DirectPTEFlags};
|
||||
end else begin
|
||||
assign DirectInstrPTE = {10'b0, PCPageNumber, DirectPTEFlags};
|
||||
assign DirectMemPTE = {10'b0, MemAdrPageNumber, DirectPTEFlags};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Direct translation flops
|
||||
//flopenr #(`XLEN) instrpte(HCLK, ~HRESETn, ITLBMissF, DirectInstrPTE, PageTableEntryF);
|
||||
//flopenr #(`XLEN) datapte(HCLK, ~HRESETn, DTLBMissM, DirectMemPTE, PageTableEntryM);
|
||||
|
||||
//flopr #(1) iwritesignal(HCLK, ~HRESETn, ITLBMissF, ITLBWriteF);
|
||||
//flopr #(1) dwritesignal(HCLK, ~HRESETn, DTLBMissM, DTLBWriteM);
|
||||
|
||||
// Prefer data address translations over instruction address translations
|
||||
assign TranslationVAdr = (DTLBMissM) ? MemAdrM : PCF;
|
||||
assign MMUTranslate = DTLBMissM || ITLBMissF;
|
||||
@ -150,8 +117,6 @@ module pagetablewalker (
|
||||
if (`XLEN == 32) begin
|
||||
logic [9:0] VPN1, VPN0;
|
||||
|
||||
assign SvMode = SATP_REGW[31];
|
||||
|
||||
flopenl #(3) mmureg(HCLK, ~HRESETn, 1'b1, NextWalkerState, IDLE, WalkerState);
|
||||
|
||||
// State transition logic
|
||||
@ -160,11 +125,12 @@ module pagetablewalker (
|
||||
IDLE: if (MMUTranslate) NextWalkerState = LEVEL1;
|
||||
else NextWalkerState = IDLE;
|
||||
LEVEL1: if (~MMUReady) NextWalkerState = LEVEL1;
|
||||
// else if (~ValidPTE || (LeafPTE && BadMegapage))
|
||||
// NextWalkerState = FAULT;
|
||||
// *** Leave megapage implementation for later
|
||||
// *** need to check if megapage valid/aligned
|
||||
else if (ValidPTE && LeafPTE) NextWalkerState = LEAF;
|
||||
// *** <FUTURE WORK> According to the architecture, we should
|
||||
// fault upon finding a superpage that is misaligned or has 0
|
||||
// access bit. The following commented line of code is
|
||||
// supposed to perform that check. However, it is untested.
|
||||
else if (ValidPTE && LeafPTE && ~BadMegapage) NextWalkerState = LEAF;
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** If you test the above line, delete this line
|
||||
else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0;
|
||||
else NextWalkerState = FAULT;
|
||||
LEVEL0: if (~MMUReady) NextWalkerState = LEVEL0;
|
||||
@ -180,13 +146,12 @@ module pagetablewalker (
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
|
||||
assign MegapageMisaligned = |(CurrentPPN[9:0]);
|
||||
assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
||||
|
||||
assign VPN1 = TranslationVAdr[31:22];
|
||||
assign VPN0 = TranslationVAdr[21:12]; // *** could optimize by not passing offset?
|
||||
assign VPN0 = TranslationVAdr[21:12];
|
||||
|
||||
// Assign combinational outputs
|
||||
always_comb begin
|
||||
@ -194,7 +159,6 @@ module pagetablewalker (
|
||||
TranslationPAdr = '0;
|
||||
PageTableEntry = '0;
|
||||
PageType ='0;
|
||||
MMUTranslationComplete = '0;
|
||||
DTLBWriteM = '0;
|
||||
ITLBWriteF = '0;
|
||||
WalkerInstrPageFaultF = '0;
|
||||
@ -217,13 +181,11 @@ module pagetablewalker (
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00;
|
||||
MMUTranslationComplete = '1;
|
||||
DTLBWriteM = DTLBMissM;
|
||||
ITLBWriteF = ~DTLBMissM; // Prefer data over instructions
|
||||
end
|
||||
FAULT: begin
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
|
||||
MMUTranslationComplete = '1;
|
||||
WalkerInstrPageFaultF = ~DTLBMissM;
|
||||
WalkerLoadPageFaultM = DTLBMissM && ~MemStore;
|
||||
WalkerStorePageFaultM = DTLBMissM && MemStore;
|
||||
@ -248,13 +210,10 @@ module pagetablewalker (
|
||||
end else begin
|
||||
localparam LEVEL2 = 3'h5;
|
||||
|
||||
assign SvMode = SATP_REGW[63];
|
||||
|
||||
logic [8:0] VPN2, VPN1, VPN0;
|
||||
|
||||
logic GigapageMisaligned, BadGigapage;
|
||||
|
||||
// *** Do we need a synchronizer here for walker to talk to ahblite?
|
||||
flopenl #(3) mmureg(HCLK, ~HRESETn, 1'b1, NextWalkerState, IDLE, WalkerState);
|
||||
|
||||
always_comb begin
|
||||
@ -262,14 +221,21 @@ module pagetablewalker (
|
||||
IDLE: if (MMUTranslate) NextWalkerState = LEVEL2;
|
||||
else NextWalkerState = IDLE;
|
||||
LEVEL2: if (~MMUReady) NextWalkerState = LEVEL2;
|
||||
else if (ValidPTE && LeafPTE) NextWalkerState = LEAF;
|
||||
// *** <FUTURE WORK> According to the architecture, we should
|
||||
// fault upon finding a superpage that is misaligned or has 0
|
||||
// access bit. The following commented line of code is
|
||||
// supposed to perform that check. However, it is untested.
|
||||
else if (ValidPTE && LeafPTE && ~BadGigapage) NextWalkerState = LEAF;
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** If you test the above line, delete this line
|
||||
else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL1;
|
||||
else NextWalkerState = FAULT;
|
||||
LEVEL1: if (~MMUReady) NextWalkerState = LEVEL1;
|
||||
// else if (~ValidPTE || (LeafPTE && BadMegapage))
|
||||
// NextWalkerState = FAULT;
|
||||
// *** Leave megapage implementation for later
|
||||
else if (ValidPTE && LeafPTE) NextWalkerState = LEAF;
|
||||
// *** <FUTURE WORK> According to the architecture, we should
|
||||
// fault upon finding a superpage that is misaligned or has 0
|
||||
// access bit. The following commented line of code is
|
||||
// supposed to perform that check. However, it is untested.
|
||||
else if (ValidPTE && LeafPTE && ~BadMegapage) NextWalkerState = LEAF;
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** If you test the above line, delete this line
|
||||
else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0;
|
||||
else NextWalkerState = FAULT;
|
||||
LEVEL0: if (~MMUReady) NextWalkerState = LEVEL0;
|
||||
@ -296,20 +262,20 @@ module pagetablewalker (
|
||||
|
||||
assign VPN2 = TranslationVAdr[38:30];
|
||||
assign VPN1 = TranslationVAdr[29:21];
|
||||
assign VPN0 = TranslationVAdr[20:12]; // *** could optimize by not passing offset?
|
||||
assign VPN0 = TranslationVAdr[20:12];
|
||||
|
||||
// *** Should translate this flop block into our flop module notation
|
||||
always_comb begin
|
||||
// default values
|
||||
TranslationPAdr = '0;
|
||||
PageTableEntry = '0;
|
||||
PageType = '0;
|
||||
MMUTranslationComplete = '0;
|
||||
DTLBWriteM = '0;
|
||||
ITLBWriteF = '0;
|
||||
WalkerInstrPageFaultF = '0;
|
||||
WalkerLoadPageFaultM = '0;
|
||||
WalkerStorePageFaultM = '0;
|
||||
|
||||
// The MMU defaults to stalling the processor
|
||||
MMUStall = '1;
|
||||
|
||||
case (NextWalkerState)
|
||||
@ -331,13 +297,12 @@ module pagetablewalker (
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (WalkerState == LEVEL2) ? 2'b11 :
|
||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00);
|
||||
MMUTranslationComplete = '1;
|
||||
DTLBWriteM = DTLBMissM;
|
||||
ITLBWriteF = ~DTLBMissM; // Prefer data over instructions
|
||||
end
|
||||
FAULT: begin
|
||||
// Keep physical address alive to prevent HADDR dropping to 0
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
MMUTranslationComplete = '1;
|
||||
WalkerInstrPageFaultF = ~DTLBMissM;
|
||||
WalkerLoadPageFaultM = DTLBMissM && ~MemStore;
|
||||
WalkerStorePageFaultM = DTLBMissM && MemStore;
|
||||
@ -129,6 +129,7 @@ module tlb #(parameter ENTRY_BITS = 3,
|
||||
assign Translate = SvMode & (PrivilegeModeW != `M_MODE);
|
||||
|
||||
// Determine how the TLB is currently being used
|
||||
// Note that we use ReadAccess for both loads and instruction fetches
|
||||
assign ReadAccess = TLBAccessType[1];
|
||||
assign WriteAccess = TLBAccessType[0];
|
||||
assign TLBAccess = ReadAccess || WriteAccess;
|
||||
@ -179,7 +180,6 @@ module tlb #(parameter ENTRY_BITS = 3,
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// *** Not the cleanest solution.
|
||||
// The highest segment of the physical page number has some extra bits
|
||||
// than the highest segment of the virtual page number.
|
||||
localparam EXTRA_PHYSICAL_BITS = `PPN_HIGH_SEGMENT_BITS - `VPN_SEGMENT_BITS;
|
||||
|
||||
@ -1,35 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// tlb_rand.sv
|
||||
//
|
||||
// Written: jtorrey@hmc.edu & tfleming@hmc.edu 16 February 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Outputs a random index for writing to the TLB.
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
module tlb_rand #(parameter ENTRY_BITS = 3) (
|
||||
input clk, reset,
|
||||
output [ENTRY_BITS-1:0] WriteIndex
|
||||
);
|
||||
|
||||
logic [31:0] data;
|
||||
assign data = 32'b0;
|
||||
assign WriteIndex = data[ENTRY_BITS-1:0];
|
||||
|
||||
endmodule
|
||||
@ -71,7 +71,7 @@ module pmpadrdec (
|
||||
generate
|
||||
if (`XLEN == 32 || `XLEN == 64) begin
|
||||
// priority encoder to translate address to range
|
||||
// *** We'd like to replace this with a
|
||||
// *** We'd like to replace this with a better priority encoder
|
||||
// *** We should not be truncating 64 bit physical addresses to 32 bits...
|
||||
always_comb
|
||||
casez (CurrentPMPAdr[31:0])
|
||||
|
||||
@ -150,17 +150,6 @@ module pmpchecker (
|
||||
Match && L_Bit && InvalidRead :
|
||||
EnforcePMP && InvalidRead;
|
||||
|
||||
/*
|
||||
assign PMPInstrAccessFaultF = 1'b0;
|
||||
assign PMPStoreAccessFaultM = 1'b0;
|
||||
assign PMPLoadAccessFaultM = 1'b0;
|
||||
*/
|
||||
|
||||
/*
|
||||
If no PMP entry matches an M-mode access, the access succeeds. If no PMP entry matches an
|
||||
S-mode or U-mode access, but at least one PMP entry is implemented, the access fails.
|
||||
*/
|
||||
|
||||
assign PMPSquashBusAccess = PMPInstrAccessFaultF || PMPLoadAccessFaultM || PMPStoreAccessFaultM;
|
||||
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user