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Updates to muldiv.sv for 32-bit div/rem

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This commit is contained in:
James E. Stine 2021-06-01 15:31:07 -04:00
parent fe22fd2db8
commit 2eeb12c674
3 changed files with 7 additions and 7 deletions
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2
wally-pipelined/config/rv64ic/wally-config.vh
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@ -31,7 +31,7 @@
`define XLEN 64
// MISA RISC-V configuration per specification
`define MISA (32'h00000104 | 0 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
`define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)

2
wally-pipelined/src/muldiv/muldiv.sv
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@ -76,7 +76,7 @@ module muldiv (
assign Den0 = W64E ? {{32{SrcBE[31]&signedDivide}}, SrcBE[31:0]} : SrcBE;
end else begin // RV32 has no W-type instructions
assign Num0 = SrcAE;
assign Den0 = SrcAE;
assign Den0 = SrcBE;
end
// capture the Numerator/Denominator

10
wally-pipelined/testbench/testbench-imperas.sv
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@ -320,11 +320,11 @@ string tests32f[] = '{
"rv32m/I-MUL-01", "2000",
"rv32m/I-MULH-01", "2000",
"rv32m/I-MULHSU-01", "2000",
"rv32m/I-MULHU-01", "2000"
//"rv32m/I-DIV-01", "2000",
//"rv32m/I-DIVU-01", "2000",
//"rv32m/I-REM-01", "2000",
//"rv32m/I-REMU-01", "2000"
"rv32m/I-MULHU-01", "2000",
"rv32m/I-DIV-01", "2000",
"rv32m/I-DIVU-01", "2000",
"rv32m/I-REM-01", "2000",
"rv32m/I-REMU-01", "2000"
};
string tests32ic[] = '{