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Fixed issue with not saving the first cache block read on a miss spill.

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This commit is contained in:
Ross Thompson 2021-04-26 12:57:34 -05:00
parent ee628e388a
commit afbb100860
1 changed files with 3 additions and 3 deletions
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6
wally-pipelined/src/ifu/icache.sv
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@ -496,14 +496,14 @@ module icachecontroller #(parameter LINESIZE = 256) (
NextState = STATE_MISS_SPILL_READ1;
end
STATE_MISS_SPILL_READ1: begin // always be a hit as we just wrote that cache block.
PCMux = 2'b10; // there is a 1 cycle delay after setting the address before the date arrives.
spillSave = 1'b1; /// *** Could pipeline these to make it clearer in the fsm.
PCMux = 2'b01; // there is a 1 cycle delay after setting the address before the date arrives.
ICacheReadEn = 1'b1;
NextState = STATE_MISS_SPILL_2;
end
STATE_MISS_SPILL_2: begin
PCMux = 2'b10;
UnalignedSelect = 1'b1;
UnalignedSelect = 1'b1;
spillSave = 1'b1; /// *** Could pipeline these to make it clearer in the fsm.
if (~hit) begin
CntReset = 1'b1;
NextState = STATE_MISS_SPILL_MISS_FETCH_WDV;